This is Part 3 of a short Memory Guy series in which contributor Ron Neale continues to explore the possible future impact on PCM memory performance, especially write/erase endurance, building on the results of the IBM/Yale University analysis outlined in Part 1 and Part 2.
Part 3 of this series of articles triggered by the recently published PCM device analysis by a team from IBM/Yale University, moves to a look at its possible implications for the arsenic doped GST threshold switch. Although the threshold switch was not part of the IBM/Yale work, the implementation of the call for bipolar operation of PCMs means there will be a requirement for a threshold switch whose durability matches that of the memory with which it will be associated in a memory array.
If the study’s finding for PCM can be applied to the arsenic-doped GST threshold switch which is used in today’s commercially-available PCM arrays then the threshold switch might just be the weak link that accounts for the poor endurance of commercial PCM memory arrays.
One little conundrum we must address is: Which Continue reading “Extending the Write/Erase Lifetime of Phase Change Memory: Part 3 – Failure Modes for the Threshold Switch”
This is Part 2 of a short Memory Guy series in which contributor Ron Neale continues to explore the possible future impact on PCM memory performance, especially write/erase endurance, building on the results of the IBM/Yale University analysis outlined in Part 1.
After, in Part 1, summarizing the methodology my next step was to try to bring together in another simple diagram all the detail of the complexity of the movement of the different elements of the phase change memory material at different locations within the memory cell which the IBM/Yale work has disclosed. Movement which leads to the conclusion that bi-polar operation would be means of extending PCM endurance.
In this post’s first diagram (below) the central region provides illustration of the paper’s unique PCM device structure: A high aspect ratio tapered cell lined with a metal conductor. With the two-state memory switching region located (red coloured) roughly at the centre of the taper. This means that, Continue reading “Extending the Write/Erase Lifetime of Phase Change Memory: Part 2 – A More Complete View of Element Separation”
This is the first of a new line-up of Memory Guy posts by Ron Neale. In this 4-part series Ron takes a look at the recently-published analysis by a team from IBM and Yale University (Wiley: Communications of Advanced Materials, Volume 30, Issue 9, March 1, 2018 “Self-Healing of a Confined Phase Change Memory Device with a Metallic Surfactant Layer,” Xie et al) which has cast some new light on the complexity of the movement and element separation in phase change memory (PCM) device structures.
In this series of articles I will briefly review what I think is an important piece of work and its implications for the future of PCM write/erase (w/e) endurance in commercial PCM memory arrays. Today’s production Phase-Change Memory, the basis of the Intel/Micron 3D XPoint Memory, wears out faster than expected. This series will investigate some of the potential reasons for this discrepancy.
Back in 2016 a research team led by IBM claimed the world record for PCM w/e endurance of greater than 2 x 10E12 cycles (ALD-based Confined PCM with a Metallic Liner Toward Unlimited Endurance, Proc IEDM 2016 ). As of today commercially available PCM memory arrays offer w/e endurance of some six orders of magnitude less. The table below Continue reading “Extending the Write/Erase Lifetime of Phase Change Memory: Part 1- PCM Element Separation and Endurance”
There has been a lot of discussion in the trade press lately about new memory technologies. This is with good reason: Existing memory technologies are approaching a limit after which bits can’t be shrunk any smaller, and that limit would put an end to Moore’s Law.
But there are even more compelling reasons for certain applications to convert from today’s leading technologies (like NAND flash, DRAM, NOR flash, SRAM, and EEPROM) to one of these new technologies, and that is the fact that the newer technologies all provide considerable energy savings in computing environments.
Objective Analysis has just published a white paper that can be downloaded for free which addresses a number of these technologies. The white paper explains why energy is wasted with today’s technologies and how these new memory types can dramatically reduce energy consumption.
It also provides a Continue reading “Latest White Paper: New Memories for Efficient Computing”
For a number of years The Memory Guy has wanted to find a copy of the 1970 article, published in Electronics magazine, in which Intel’s Gordon Moore and two authors from Energy Conversion Devices, Ron Neale and D.L. Nelson, showed that PCM could be used as a memory device. After all, this is the technology behind Micron & Intel’s 3D XPoint Memory.
The cover of the magazine (this post’s graphic) has been used by Intel to promote its PCM or PRAM chips before those were spun off to Numonyx (now a part of Micron). Intel, though, didn’t appear to have anything to share but the cover photo.
Electronics magazine went out of business in 1995, and that makes the task of finding archive copies more challenging.
It recently occurred to me that the best person to ask might be the article’s lead author, Ron Neale, who has been a regular contributor to EE Times and who now also contributes blog posts to The Memory Guy.
I was astounded to discover that Continue reading “Original PCM Article from 1970”
At a technical conference hosted by the IEEE this week IBM announced the results of nearly a decade of research in which its scientists have been investigating the emerging technology known as “Phase Change Memory” (PCM). The scientists presented a means of successfully storing three bits per cell for the first time, while also addressing all of PCM’s challenging idiosyncrasies, including resistance drift and temperature drift.
Commonly referred to by the erroneous nickname “TLC” for Triple Level Cell, this technology squeezes three bits of data into the space of a single bit, essentially cutting the cost per gigabyte to about one third of that of a standard memory chip making it closer in cost to flash.
With this step IBM expects to help drive a new memory layer into existence, one that will fit between the cheap and slow NAND flash used in SSDs and the fast but expensive DRAM used for main memory. Such a layer would improve the cost/performance of all types of Continue reading “IBM Jumps on the “New Memory” Bandwagon”
The Memory Guy was recently asked about using memories in a satellite. What would be a good technology to use in a space application?
The problem with space is that there is a lot of radiation. Radiation on the earth’s surface is lower because it is stopped by the atmosphere, but in space there is an abundance of radiation that interferes with most semiconductors. Radiation is also a concern in certain medical applications where a memory must maintain its contents while undergoing sterilization through irradiation. Experiments on conventional flash memories have shown data loss at only 2% of the Continue reading “Memory Issues in Space & Medical Applications”
Some time ago The Memory Guy was asked by Numonyx (later acquired by Micron) to put together an online course for EE Times on memory technologies, explaining how each one works and where it is used.
Although the course was very well received, I never posted a link to it on The Memory Guy blog. This post is intended to correct that error.
The course runs 75 minutes and covers the basics of DRAM, non-volatile RAM, SRAM, NAND flash, NOR flash, mask ROM, and EEPROM. It explains each technology’s advances in size, cost and performance, leading up to the development of Continue reading “Fundamentals of Memory – Free Online Course”
Lane Mason of Objective Analysis recently shared with The Memory Guy an article he wrote for the 4 April 2007 Denali Memory Report covering Phase Change Memory (PCM or PRAM.) It looked like something big was about to happen with the technology: PCM looked nearly ready to enter production.
The article included an excerpt of an EE Times interview with Micron’s CEO, the late Steve Appleton, in which Appleton stated that PCM advocates threatened to take over the memory market in 2000.
Here it is 2012, and PCM represents little more than a drop in the bucket when it comes to memory sales, although Continue reading “Alternative Memory Technologies Patiently Wait For Market to Explode”
After years of prototyping Micron Technology claims to be the first to introduce production volumes of Phase-Change Memory, or PCM. This memory, also known as PRAM, has long been positioned as a contender to replace flash once flash reaches its scaling limit. Rather than use electrons to store a bit, PCM uses a type of glass that is conductive when in a crystalline state and resistive when amorphous, two states that are relatively easy to control. The size of the bits can shrink to a very small dimensions, allowing PCM to scale into the single-digit number of nanometers, which most folks today believe to be beyond the realm of flash.
This product began its life at Intel, then followed the Numonyx spin-off, and was taken over by Micron when it acquired Numonyx. In fact, Intel got into PCM very early on – this post’s graphic is the cover of an Electronics Magazine from September 1970 with an Intel story, written by Gordon Moore, telling about a 128-bit PCM research chip.
So far only three companies have produced samples Continue reading “Micron PCM Enters Mass Production”