An acquaintance recently brought to my attention an article in R&D Magazine about some pioneering research on phase-change memories or PCM. The researchers’ findings hold a lot of promise. (R&D Magazine’s article is based upon an original paper in the journal Science.)
A team led by Ritesh Agarwal, associate professor at the University of Pennsylvania, was trying to develop a better understanding of the mechanism behind the phase changes in PCM. The team found that existing programming algorithms that involve melting the material could be replaced with pulses of electrical current that not only would program the cell without heat, but provided an “On” to “Off” resistance ratio of 2-3 orders of magnitude, which renders the cell significantly easier to read, especially in the presence of noise. This effectively makes memory chip design Continue reading “A New Way to Build Phase-Change Memory (PCM)”
Everyone knows that flash memory is about to hit its scaling limit – it’s right around the corner. We’re ready for it because it’s been right around the corner for more than a decade now. It’s so close we can taste it.
When will it happen?
One thing that is quite clear is that nobody knows when NAND flash will stop scaling. Everyone knows that it’s soon, but researchers continue to find ways to push the technology another couple of process nodes past where anyone thought it could possibly go, and they have been doing this since Continue reading “The End of Flash Scaling”
The IEEE Spectrum published an interesting article postulating that Russia’s recently-failed Mars probe may have suffered from bad memory chips. According to the Spectrum article the Russian government’s Official Accident Investigation Results faulted SRAMs:
The report blames the loss of the probe on memory chips that became fatally damaged by cosmic rays.
Both the main computer and the backup computer seem to have failed at the same time, Continue reading “IEEE Spectrum: Did Bad Memory Chips Down Russia’s Mars Probe?”
During this week’s International Solid State Circuits Conference (ISSCC) I learned some very valuable information about memories built using crosspoint matrices.
Since ISSCC is a conference at which you meet the best and brightest minds in the industry it should come as no surprise that I was able to meet with several of the most forward-thinking industry luminaries. One of them explained to me a very fundamental difficulty with resistive RAMs (ReRAMs): These devices require a forward current to be programmed to a “1” and a reverse current to be set to a zero. This goes against the ideal crosspoint memory design in which a bit would consist of nothing more than a diode in series with a memory element. By inserting a diode, the current can only run in one direction, so a bit can be programmed or it can be erased, but not both. This is called Continue reading “How Do You Make a ReRAM Work?”