Tag: scaling

DRAM Inventor Wins Kyoto Prize

Dr. Robert Dennard Receiving the Kyoto Advanced Technology Prize. Source: The Inamori FoundationThis year’s Kyoto Prizes included an Advanced Technology Prize for the father of DRAM, IBM’s Dr. Robert Dennard.

The Kyoto Prize, one of the world’s most prestigious accolades, is an international award bestowed once a year by The Inamori Foundation to honor those who have contributed significantly to the scientific, cultural and spiritual betterment of humankind.  Some say it is similar to the Nobel Prize, and seven Kyoto Prize laureates have gone on to win the Nobel Prize.

In addition to the kudos of receiving this honor, Denning was also Continue reading “DRAM Inventor Wins Kyoto Prize”

Samsung Announces 3D NAND Production

Toshiba's BiCS 3D NAND 2007 diagramSamsung has announced production of its 3D NAND technology.  This approach, first introduced by Toshiba in 2007, allows NAND flash makers to achieve more bits per chip by building NAND strings, which normally run across the surface of the chip, as vertical stacks.

It’s a fascinating technology, since it harnesses exotic steps invented by DRAM makers in the 1990s to get over scaling problems in that technology.  At the time DRAM had to go vertical to follow Moore’s Law and there were two schools of vertical DRAM: Stacked Capacitor, and Trench Cell.  The stacked capacitor camp layered polysilicon and silicon dioxide into layers to form a vertical capacitor.  The trench camp etched a very narrow and deep hole into the silicon and lined it with the capacitor plates.  Both worked very well, but over time the trench makers have Continue reading “Samsung Announces 3D NAND Production”