In this post contributor Ron Neale looks deeper into a paper delivered by CEA-Leti at December’s 2019 IEDM conference, evaluating its fundamental thesis that an OTS selector is suitable for high-density memory arrays. Another interesting aspect of this same paper was the subject of an earlier post.
One eye catcher at IEDM 2019 was a paper from a team in France at CEA-Leti, Minatec, Grenoble, IMEP LAHC CNRS and INL CNRS, INSA Lyon, by D. Alfaro Robayo et al titled: Reliability and Variability of 1S1R OxRAM-OTS for High Density Crossbar Integration. I discussed another aspect of Continue reading “Chalcogenide Selectors and Oxide Memory Move Towards 1Gbit”
During this week’s International Solid State Circuits Conference (ISSCC) I learned some very valuable information about memories built using crosspoint matrices.
Since ISSCC is a conference at which you meet the best and brightest minds in the industry it should come as no surprise that I was able to meet with several of the most forward-thinking industry luminaries. One of them explained to me a very fundamental difficulty with resistive RAMs (ReRAMs): These devices require a forward current to be programmed to a “1” and a reverse current to be set to a zero. This goes against the ideal crosspoint memory design in which a bit would consist of nothing more than a diode in series with a memory element. By inserting a diode, the current can only run in one direction, so a bit can be programmed or it can be erased, but not both. This is called Continue reading “How Do You Make a ReRAM Work?”