3D NAND presents an interesting conundrum. To improve bit costs and continue along the path of Moore’s Law the layer count must increase. Unfortunately 3D NAND can’t benefit from lithographic scaling; it’s pretty much stuck at 40nm design rules forever. The natural way to reduce costs and increase chip density is by adding layers.
But adding layers increases the size of the staircase structure used to access the wordline layers.
With today’s structures, the addition of layers means adding stairs to the staircase – if you double the number of layers then the amount of die area required by the staircase doubles. At some point the staircase becomes so large that the die has fewer GB/mm² than a die with half as many layers.
An example of a staircase structure can be seen in the Continue reading “Solving 3D NAND’s Staircase Problem”