Tag: Terabit Cell Array Transistor

New Materials Solve Key 3D NAND Issue

imec III-V 3D NAND channelAt the IEEE’s IEDM conference last week Belgian research consortium imec showed an improved “gate first” 3D NAND that replaced the conventional polysilicon channel with InGaAs, Indium Gallium Arsenide, a III-V material.  This new technique opens the door to higher layer counts in 3D NAND, allowing denser parts to be made in support of further cost reductions.

For those unfamiliar with the term, the “gate first” approach is the foundation of Toshiba’s BiCS NAND, and presumably Micron’s floating gate 3D NAND.

imec explains that “Replacing poly-Si as a channel material is necessary, as it is not suitable for long-term scaling.”  Further they report that on-state current (ION) and transconductance (gm) of the III-V channel was better than that of polysilicon devices, without any programming, erase, or endurance degradation.  The device’s characteristics are shown in this post’s graphic.

The consortium reports that the current through the Continue reading “New Materials Solve Key 3D NAND Issue”

How Do You Erase and Program 3D NAND?

How FN Tunneling WorksSome of my readers have asked: “How is 3D NAND programmed and erased?  Is it any different from planar NAND?”

In a word: No.

(Before I get too far into this allow me to admit that The Memory Guy doesn’t understand quantum physics, so I will be presenting this only to the depth that I understand it.  There will be no band-gap diagrams or equations to wrestle with.)

Both 3D NAND and planar NAND use Fowler Nordheim Tunneling (FN) to both program and erase.  This differs from NOR flash which programs bits using Continue reading “How Do You Erase and Program 3D NAND?”