Intel has recently announced a technology that the company calls PowerVia that could inadvertently help reduce the cost of HBM – high-bandwidth memory.
HBM is a stack of up to twelve DRAM chips that are interconnected using over one thousand TSVs – Through-Silicon Vias. These are metal-filled holes etched right through the DRAM die to allow signals to move vertically through the chip. It’s an alternative to more conventional wire bonding.
HBM sells for significantly more than Continue reading “Could Intel’s PowerVia Lower HBM Costs?”
Today Micron Technology announced that it is sampling the Hybrid Memory Cube (HMC) a DRAM packaging technology that it has been working on with the HMC Consortium.
Micron has been pushing to rapidly advance the HMC’s development and seems to have reached this point in an impressively brief time, given the complexity of the technology. It has only been two years since the first public appearance of the HMC at the 2011 Intel Developer Forum.
Some pretty advanced technology was used to make this product. DRAM processes are not very good at Continue reading “Micron Samples Hybrid Memory Cube”
In a December 1 press release IBM announced that the company will be manufacturing Micron Technology’s Hybrid Memory Cube (HMC) which IBM claims to be “the first commercial CMOS manufacturing technology to employ through-silicon vias (TSVs).”
This device is one that Altera, Intel, Micron, Open Silicon, Samsung, and Xilinx have all presented recently as a plausible solution to the difficulty of increasing the speed of DRAM/processor communications. The Hybrid Memory Cube Consortium (HMCC) website offers a deep dive into the details of the consortium and the technology.
Continue reading “IBM to Build Micron Hybrid Memory Cube”