Intel has recently announced a technology that the company calls PowerVia that could inadvertently help reduce the cost of HBM – high-bandwidth memory.
HBM is a stack of up to twelve DRAM chips that are interconnected using over one thousand TSVs – Through-Silicon Vias. These are metal-filled holes etched right through the DRAM die to allow signals to move vertically through the chip. It’s an alternative to more conventional wire bonding.
HBM sells for significantly more than Continue reading “Could Intel’s PowerVia Lower HBM Costs?”
At a Conference in San Francisco today (Tuesday December 13 ) ST-Ericsson and CEA-Leti presented a paper on something the companies called a: “Breakthrough 3DIC with Wide I/O Interface.”
This product appears to be a variation on the Hybrid Memory Cube, or HMC concept detailed in a prior post.
Remember that the HMC stacks a number of DRAM chips atop a logic chip. The memories store data and communicate to the logic chip through thousands of through-silicon vias (TSVs) while the logic chip handles communications with the outside world. Continue reading “WIOMING: Another Spin on the Hybrid Memory Cube”