Tag: vertical NAND

Finally! Samsung’s 3-Bit V-NAND Arrives

3-bit V-NANDSamsung has finally introduced the 3-bit 3D NAND chip it revealed at last August’s Flash Memory Summit.  This announcement was made in the form of an SSD announcement.

For those who were unable to attend the Flash Memory Summit, Samsung’s Senior VP of Memory R&D, Bob Brennan, announced in his keynote speech that a 3D 32-layer V-NAND, a chip that would achieve twice the chip density of planar NAND, was entering production and that SSDs would follow in a month.  Now, two months later, Samsung has announced those SSDs.

This week’s release reiterates Continue reading “Finally! Samsung’s 3-Bit V-NAND Arrives”

Why NAND is So Difficult to Scale

ASML chart chowing the lithography used for 4X, 3X, 2X, and 1Xnm planar NAND and 3D NANDNAND flash is the process leader in memory technology, and this puts it in a very challenging position: It must ramp to high volume production using techniques that have never been tried before.

The graphic for this post (click to enlarge), supplied by ASML, the semiconductor industry’s leading lithography tool supplier, illustrates the challenge of migrating from one process node to the next.  Across the bottom, on the X-axis, are representative process nodes ranging from “2D-45”, or two-dimensional (planar) 45nm NAND, to “3D-5x”, or three-dimensional 5xnm NAND.  Below these numbers are the year of volume production.

The vertical axis, labeled “Tolerance” represents the minimum Continue reading “Why NAND is So Difficult to Scale”