One of the thornier problems in making 3D NAND is the job of connecting the peripheral logic (the row decoders) to all of those control gates that are on layers buried somewhere within the bit array. Remember that the control gates are the conductive sheets of polysilicon or tantalum nitride at various depths in the chip.
The problem boils down to this: You can’t run connections from each layer up or down the side of the chip to get to the CMOS circuits below. Instead you have to create a terrace structure to expose and connect to each layer.
These connections are made by etching a stair-step pattern into the layers and sinking Continue reading “3D NAND: How do You Access the Control Gates?”
My prior 3D NAND post explained how Toshiba’s BiCS cell works, using a silicon nitride charge trap to substitute for a floating gate. This post will look at an alternative technology used by Samsung and Hynix which is illustrated in the first graphic, a diagram Samsung presented at a technical conference. This cell also uses a charge trap.
Let The Memory Guy warn you, if the process in my prior post seemed tricky, this one promises to put that one to shame!
Part of this stems from the use of a different kind of NAND bit cell. You can shrink flash cells smaller if you use a high-k gate dielectric (one with a high dielectric constant “k”) since it Continue reading “An Alternative Kind of Vertical 3D NAND String”