Tectonic Change Coming to Chip Production

Drawing of a log rotating on a lathe being cut into veneerEvery so often a new idea comes into an established industry from an unexpected direction and creates a dramatic change to the way that the industry operates.  In today’s post The Memory Guy will explain a radical new chip production process will rapidly change the nature and cost structure of the entire semiconductor industry, DRAM and NAND flash first, slashing costs and waste while phenomenally increasing output.

This revolutionary approach stems from none other than Australia’s plywood industry.  Dr. Afferbeck Lauder, noted author and the idea’s champion, realized that the chip market was enormously wasteful and was tied to what he refers to as: “An archaic scheme of batch processing.”  He noted that certain chips start with a raw wafer of extremely pure silicon 750-800μm thick, that is processed into chips and subsequently back-ground to as little as 30µm.  “Name one other industry that saves only 1/25th of a costly highly-refined raw material and simply discards the rest,” he said.  “It’s astoundingly inefficient and it’s shamefully wasteful.”

Lauder, who hails from the city of Townsville, Queensland, is the president of Australia’s National Plywood Board, a combination of a trade group and political party.  When the organization discovered that the automation that it advocates reduces the industry’s employment, lessening the size of its voting bloc, Dr. Lauder shifted his focus to the semiconductor industry which was experiencing critical shortages in 2021.  “Chip makers have a lot to learn about efficient mass production,” he said.  “The techniques used for plywood production are a perfect fit for semiconductors.  Today’s chip shortage can be ended once and for all.”

Photo of a 300mm diameter ingot of pure silicon, ready to be sawn into wafers.“The problem is one of mindset,” he says.  “Plywood manufacturers think in millions of square meters. Chip makers think in terms of 300mm wafers full of nanometer-scale devices.  They need to think bigger.  When you think big, efficiencies follow.”

Dr. Lauder points out that today’s silicon wafers are sawn laterally from large round ingots like the one shown to the left (courtesy of Wikimedia Commons).  Conventional processing requires for these wafers to be at least 750μm thick to make them sufficiently stiff to withstand processing.  Yet many of these wafers, particularly those used for memory chips, are back-ground after processing so that they can be stacked, either as High-Bandwidth Memory packages (HBM), in the case of DRAM, or as very high-capacity NAND devices.  These back-ground wafers range from 75μm all the way down to 30μm in thickness.

Photo of a processed semiconductor wafer curled in a tight tube about 10mm in diameterLauder notes that: “When wafers get that thin they become very flexible.  I saw this picture and immediately realized that their flexibility lent them to roll-to-roll processing, which is one of the cheapest forms of manufacture.  It’s used in extreme-high-volume production for things like newspapers and textiles.”  His idea is to saw the ingot radially into one very long sheet, the same way that veneer is peeled from a log in plywood production, and then to employ roll-to-roll processing to pattern the chips onto the silicon.

Diagram of a log spinning on a lathe, as a knife peels off a sheet of veneerToday’s silicon ingots are about 600mm long and 300mm in diameter.  If that wafer is sawn to a 30µm sheet, even if 45µm is lost in the process, the entire ingot should be able to produce a single sheet over 900 meters in length with an area of more than one half km².  Lauder notes that this is the same as 50 billion square centimeters, and according to SEMI the entire semiconductor industry used only 14.165 billion square inches or 91.4 billion cm² of silicon in 2021, so the industry’s needs could be entirely fulfilled with the sheets produced by only two ingots.

Plus, the total silicon area is more efficiently used.  “You have to waste a lot of space towards the wafer edge if you’re making rectangular chips on a round wafer,” he explained.  “A roll-to-roll approach uses every square millimeter of these completely-rectangular sheets of silicon.”

The sketch below illustrates a small portion of the envisioned fab (click to enlarge).  “We can’t call it a wafer fabrication plant, because there aren’t any wafers,” says Dr. Lauder.  The process uses relatively conventional tools with the exception of the bandsaw, which will require special engineering to meet the required tolerance.

Diagram of a roll-to-roll print process, with blocks indicating asemiconductor processing tools working on a sheet of silicon

The process substitutes nano-imprint lithography for more conventional optical lithography because nano-imprint lithography is better suited to a roll-to-roll continuous-process model.  It also eliminates the reticle limit that is driving today’s movement to chiplets.  A single chip can be as large as the entire roll’s area.

The idea does present certain challenges.  As the ingot is turned, the orientation of the sheet’s crystals varies, a fact that will need to be addressed by more sophisticated device and process engineering.  Also, there is the issue of moving the sheet into and out of deposition and etch chambers which use controlled atmospheres or even vacuums.  Lauder lauds the extreme ingenuity that the semiconductor industry has historically employed to move past prior problems, and says that he expects for solutions to be found.

Waste might be further reduced by eliminating the saw and employing a technique developed for solar cell production where oxygen atoms are implanted below the silicon’s surface.  When the implanted area is heated, the top layer of silicon pops off the bulk material.  This idea is under careful consideration.  A single ingot could produce more than twice as much area, and thus satisfy the entire semiconductor market.

All in all, it’s stunningly brilliant idea, like so many others that The Memory Guy has been lucky enough to bring to my readers’ attention on the first of every April,


4 thoughts on “Tectonic Change Coming to Chip Production”

  1. With respect to Dr. Lauder, I can see a number of process optimizations he may have missed because they aren’t used in the lumber industry. For example, a scanned high-power laser (like those used in laser printers) could skive the emerging sheet from the rotating boule with minimal kerf loss. The laser could also simultaneously anneal the sheet to solve the crystal orientation problem.

    With all the interest in wafer-scale integration these days, there must be almost unlimited funding available to develop this vastly superior technology. Cerebras is valued at over $4 billion for its 46,225 mm^2 “Wafer Scale Engine” for artificial intelligence processing. It should be easily possible to build a “Roll Scale Engine” at least a thousand times larger to achieve a company valuation in excess of $4 trillion.

    Kidding aside, of course, solar cells are already fabricated using roll-to-roll processing of thin-film silicon deposited on steel foil.

    1. Peter,

      Your reply is amazingly on-target!

      The difference between this and solar, though, is that the National Plywood Board approach is monocrystalline, and requires no steel foil, so IC silicon should be less costly than solar silicon.

      I spoke with Dr. Lauder, and he is fascinated with your notion of skiving the sheet to solve the crystal orientation issue. He asked for me to extend an employment offer. Mind contacting him directly?

      Thanks for the comment!


      The Memory Guy

        1. Steve,

          Yes it is. It’s no coincidence that both were posted on the same day, or that the “Flash as Tape” post links to this one.

          Lauder’s innovation is an enabling technology for the eGAD invention.

          These are exciting times, with drastic change right around the corner.

          Thanks for the comment!


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