In this post in The Memory Guy blog, the first of a 2-part series, Ron Neale returns to explore the present state-of-play for chalcogenide-based switching and memory, with a plea for continuation of research. Along the way he invokes a three-point law for determining the probability of success for would be emerging memory entrepreneurs.
Does PCM still have a chance to become an important new memory technology? Intel’s abandonment of their Optane memory project, while sad, after so much effort and expense, does not and should not mark the end of the road for chalcogenide material-based switching devices and PCM.
There is a need to continue research and development work on switching effects in chalcogenide-based materials. The tree chart below is my starting point for making a case for this, and summarises what might be described as the present state-of-play.
Intel’s 3D XPoint Memory
Each of Intel’s memory cells illustrated below had two chalcogenide-based devices, the phase change memory (in green) and a threshold switch (yellow). It is the latter, acting as a matrix isolation device or selector which deserves more research attention as far as future emerging memory development is concerned.
As memory matrix isolation devices, chalcogenide-based threshold switches offer a thin film solution for memory devices requiring either unidirectional or bidirectional current flow, ReRAMs would be one example of the latter.
On the extreme left-hand side of the tree chart, one of the two blocks serves as a reminder that phase change memory has characteristics that make it a natural nonvolatile integrating device, essential for those pursuing AI, neuromorphic and brain-gate interests.
Also shown, and to complete the tree chart on the extreme left, is a reminder that the PCM also has the unique, easy-to-use ability to take the load off the processor with in-memory multiplication and addition.
At this juncture readers might be tempted to raise the question that PCM and threshold switch amorphous chalcogenide alloys have been in development for 50 or more years, by now surely most questions have been answered. “Not so,” would be my answer and here is the first part of my two-part answer from those with present day hands-on experience in the memory industry.
Some Real Examples
From the tree chart three companies Weebit Nano, Symetrix, and Cerfe Labs can be used to illustrate the point.
The first was a statement made late last year by Coby Hanoch, CEO of Weebit Nano, Israel, in highlighting some of the latest developments by his team at Weebit Nano in partnership with CEA-Leti. It relates to scaling and reducing the size of the matrix isolation device in both of his company’s future memory products: small embedded and larger discrete memory arrays.
While the matrix isolation device for their first-generation 2D embedded memory arrays is a bi-directional transistor, threshold switch scaling will, as Coby stated, act for “Enabling higher packing density when the selector replaces the transistor for 2D embedded arrays”. (See the Memory Guy blog post: Emerging Memories Today: Understanding Bit Selectors.)
Coby Hanoch also reminded us that long-term success will be based on finding simple-to-use materials for threshold switches, or what might be described as process and fabrication compatible materials.
“… Developing cost-efficient selectors using only standard materials and tools is a significant challenge, but it has the potential to further minimize manufacturing cost and complexity. While additional development is still required, this new selector technology could be easily integrated into any CMOS fab, potentially enabling the high-capacity memory arrays needed while keeping size and power to a minimum…”
While the details of the new selector (which is not chalcogenide-based but uses readily-available materials) are not being disclosed, here are my best guesses of what it might be:
One matrix isolation possibility would be to use the reverse breakdown of a soft diode for writing the ReRAM from its low-resistance state (LRS) to its high-resistance state (HRS) and the forward direction for the HRS to LRS.
Or, if in a ReRAM the growth of the permanent non-volatile link is preceded by a separate threshold switching event, then for very short duration read and write pulses it might be possible to utilize that sequence for memory matrix isolation purposes. This would require a composition made from readily-available materials where the electromigration or electrostatic effects after switching or dielectric breakdown are inhibited. The memory cell would be two ReRAMs one fast and one slow. It would be the analog of the chalcogenide memory cell: a slow-crystallization GST memory element and a fast-crystallization arsenic-doped GST matrix isolation device.
Best guesses would be some type of oxide-based device, possibly an HfO-SiO-metal alloy. We will see.
In summary, what Coby Hanoch is reminding the emerging memory community is that the probability of profitable near-term success is inversely proportional to some mathematical relationship between these three key variables.
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- The number of new materials and tools required, which are not already available in existing solid state fabrication facilities.
- The number of additional fabrication steps required
- The number of device characteristics where the explanation of the underlying mechanism is debatable and lacks a clear agreed science-based understanding.
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Other Potential Applications of Chalcogenides
In two other companies, Cerfe Labs and Symetrix, there is an interesting, different selector question or challenge. Both companies have reported and demonstrated CeRAMs which are capable of operating at the extremes of the temperature range. (See the Memory Guy blog post: CeRAM Moves Front and Center on the NV Memory Stage.) They are pursuing rugged environment operation as one area of application for their memory devices. Cerfe Labs claims operation at 300°C and retention at 400°C, albeit for limited times.
For them the ability to now operate their devices at few degrees Kelvin at one end of the temperature scale and 400°C at the other end of the scale raises a question: What memory array isolation element will be used for those rugged environment temperatures – could a chalcogenide threshold switch be used? While some threshold switches are moving towards higher temperature operation, present-day detailed understanding of threshold switching still leaves questions about what might be possible.
Unlike ReRAMs, CeRAMs operate with unidirectional current flow so the opportunity to use rugged Schottky diodes or possibly even matrix isolation devices based on SiC or GaN have been suggested by representatives of companies with CeRAM interests.
There is one rugged memory environment that almost perfectly matches amorphous materials and devices based on them. It is in levels of high radiation, that is, at levels where single crystal devices are vulnerable to radiation damage from both a material and operational viewpoint.
Since many modern weapons and communications systems are dependent on satellite navigation, the need for survivable satellites with components that have been radiation hardened to strategic levels is essential, especially in times of conflict.
Combining chalcogenide-based threshold switches with SoI technology would appear to offer a perfect solution to meeting strategic radiation-hard requirements and removing the vulnerability of navigation satellites to nuclear radiation damage.
The Problems and Pitfalls
There is one very fundamental problem for those looking at the future applications for chalcogenide-based memory matrix isolation devices. It relates to bullet point three.
There is a lack of an agreed explanation of exactly how the threshold switch works. This represents a potential stumbling block and shows why more research effort is needed.
Is the underlying mechanism: electronic, thermal, or a mixture of the two? Do different compositions with similar electrical characteristics switch in the same way? Is it a solid-state effect or is melting involved as fundamental or a degenerate state? What happens during “Forming”? (See the Memory Guy blog post: NV Memory Selectors: Forming the Known Unknowns.) What is the switching time, when nucleation, over-voltage delay and recovery times are considered? The unresolved list is long.
Sure, you can adopt an engineering solution, make a device, measure its electrical characteristics, and reliability test it with stress beyond the limits to which it will be subjected. The difficulty is that without a complete science-based understanding unforeseen problems are likely to occur which spoil your plans for yield, reliability and profitability, as some large companies may have found out to their cost.
All or any of the above does not mean that the work should be abandoned. Somewhere buried in this mixture of thermal and other effects there may be hiding a simple and unique pure electronic effect with the possibility of an explanation for threshold switching based on some type of supercell super lattice-like structure. If so, that might eventually lead to a new bulk threshold switching crystalline material.
In the next part of this series, I will explore some speculative mechanisms and explore some of the different ways that the material characteristics can be linked to the same electrical switching characteristics.
