A significant transition has occurred over the past few years that many people don’t know about: Flash memory has moved almost wholesale from the floating gate bit cells, the process that they had always used before, to charge trap bit cells.
Until 2002 all flash used a floating gate. That year partners AMD & Fujitsu, who later merged their flash operations into a spin-off called Spansion, introduced a new kind of NOR flash the companies called “MirrorBit.” MirrorBit replaced the common floating gate with a charge trap.
This was a pretty revolutionary move. Prior to that time nearly all nonvolatile memory bits, EPROM, EEPROM, and NOR and NAND flash, were made using a floating gate.
The floating gate concept, invented in 1967 by Simon Sze of Bell Labs, really caught on, and is still the basis for most NOR flash and EPROM, but NAND flash has transitioned to a charge trap cell thanks, in the most part, by NAND’s move from a planar to a 3D architecture. A charge trap is easier to build in a 3D bit string (shown in this post’s graphic), as is explained in an earlier Memory Guy post.
With NAND’s transition to 3D, most NAND converted from a floating gate cell to a charge trap cell. Only partners Micron and Intel remained with a floating gate, choosing to use a more difficult process technology to obtain better-behaved flash bit cell.
After a few generations Micron, too, has elected to move to a charge trap, leaving Intel to stand on its own with this technology. This week Intel sold its NAND flash business to SK hynix. It is very likely that this will soon be followed by a conversion from floating gate to a charge trap cell.
An interesting phenomenon has occurred thanks to the fact that nearly all of today’s densest parts are made using charge trap cells: The ratio of charge trap bits to floating gate bits in production today is greater than 5:1 – over five times as many charge trap bits are now being produced as floating gate bits.
But what if we look at all of history, and count the total number of NAND flash bits that have shipped since the introduction of NAND until today? We still see that as of the end of 2019 the sum total of all charge trap NAND bits over all time surpassed the sum total of all floating gate NAND flash bits over all time. Charge trap is the clear winner.
A lot more NAND flash bits ship than do NOR flash or EEPROM, by a few orders of magnitude. This implies that the same can be safely said of all floating gate bits, that all NAND, NOR, EPROM, plus EEPROM, summed up together for all of the history of these technologies, is smaller than the sum total of all charge trap flash bits.
So how is it that people know so little about this? That’s hard to say.
The notion of using a charge trap as a memory bit was first proposed at an IEEE conference in 1967, 53 years ago. At that time a researcher at Westinghouse R&D Labs named John Szedon and his associate Ting Chu proposed that a problematic phenomenon called “Charge Trapping,” one that caused failures in the then-new MOS transistor, might be useful as a memory bit.
Until that time memory bits were made using magnetic cores, and memory arrays needed to be hand-woven, a complex and very costly procedure. Szedon and Chu proposed that charge traps could be used to replace cores, and that they could be built for a far lower cost using the new Integrated Circuit production technique.
They presented their idea at the IEEE Device Research Conference in Monterey, California, in June 1967. Unfortunately no archives were kept for this conference.
Other Westinghouse researchers took Szedon and Chu’s idea and converted it later that year into the MONOS memory element. About ten years later Fujitsu used Charge trapping in SONOS. The technology eventually was adopted for Spansion’s MirrorBit NOR flash in 2002 and, later, the 3D NAND cell that Toshiba first proposed in 2007.
3D NAND’s incredible change from floating gate to charge trap has taken place with no fanfare whatsoever.
The Memory Guy undertook to find the inventors of charge trap memory. I have been able to locate Dr. Szedon, but unfortunately his colleague, Dr. Chu, who moved from Westinghouse to the Southern Methodist University in Texas, passed away in 2017.
On behalf of the entire NAND flash business I want to thank these two luminaries, Dr. Szedon and Dr. Chu, for their priceless contribution to NAND flash and to the continuation of Moore’s Law scaling.