In this post contributor Ron Neale analyzes Weebit Nano’s recently-announced memory array, based on SiO and an Ovonic Threshold Switch selector developed by CEA-Leti in France. Ron employs his extensive background in Ovonic devices to try and sleuth out the characteristics of both the memory element and the selector, and to understand some of the inner workings of the cell.
Weebit-Nano (Hod Hasharon, Israel), have recently reported some first steps on the path they have outlined to meet their bold claim of “The Future Memory” for their SiO-based ReRAM. The first small step is the successful integration of their SiO non-volatile memory with a threshold switch selector to create a single monolithic stack for a memory cell.
Initially there are two prime product targets: large discrete memory arrays (target year 2024), and a memory module of initially a modest 128Kbits for system-on-chip (SoC) applications with a target date for silicon end of 2021. The fully-configured ReRAM module includes the 128kbit ReRAM array, control logic, decoders, I/Os (Input/Output communication elements) and error correction (ECC).
Quickly following that, and ahead of schedule, a second step was announced: the tape-out and release to fabrication of a complete monolithic single chip system for evaluation. It includes the memory module, the MCU subsystem, interfaces, interconnect, peripherals and SRAM. The chip was designed in the STMicroelectronics 130nm (f) process based on input from potential customers, which Weebit says indicated 128kbits as the optimum bit density for their analog, power, sensor and IoT designs. The move towards large discrete memory arrays will be supported by a compiler.
They join a long list of bridging filament type memory competitors, which include the Micron/Sony copper links, the silver links of Crossbar, Adesto/Dialog, Fujitsu, Panasonic, and others that to date have not amounted very much by way of commercial products, so the path to success might prove to be a mite longer than expected.
Weebit-Nano have provided some the details of their selector structure – see the inset TEM in the figure below. The other parts of the Figure are illustrations of the memory cell stack structure, based on the details so far disclosed and the earlier work of CEA-Leti for their HfO NV memory structure , . CEA-Leti have partnered with Weebit-Nano in the development of the memory cell stack.
In this illustration:
(a) Shows the as-fabricated stack with the SiO memory above the selector
(b) Illustrates the same stack after Forming, with the memory and selector in their Formed states. The memory is now also in its initial low-resistance state (LRS)
(c) Is similar but with the memory in its high resistance state (HRS).
The location of the region where memory switching occurs in the Formed oxygen vacancy column is shown close to the lower electrode. Weebit-Nano tell me they are not in a position to provide a detailed description of the shape of the filament or the location of the switching point.
An important feature of the structure is the Ti film at the Ti-SiO interface. This is described by Weebit-Nano as an “oxide vacancies enhancement” film, it might also be described as an oxygen scavenging film needed to create a reservoir of vacancies with which to build the filament. The background and explanation of the role of that important feature will be dealt with in a section below titled: “The Role of the Scavenger Film“. Oxygen vacancy-based filament NV memories are often known as OxRAMs.
The thickness dimensions for the combined SiO-Ti and the selector thickness are my estimates from earlier work. From the TEMs provided by Weebit-Nano and the earlier work of CEA-Leti, the ratio of selector-to-memory thickness is ~5.75, with apparently now a much thicker selector film than was used in CEA-Leti’s earlier and similar HfO memory stack, where the ratio is close to 1.33. Since the SEM lumps together the SiO and Ti layers it is difficult to extract the actual pristine thickness of each, although it does emphasise the important role both play in Forming or possibly even the resistance changes in the during normal memory element operation.
As the reported memory cell stack is based on 130nm lithographic node, and although the active area of the device (filament diameter) has not been disclosed, my best estimate of the area of the memory stack where the filament can form would be about 100nm square. Some projections offered by Weebit-Nano lay claim to 4f² cell areas of < 0.1µm² at the 130nm node reducing in area by 5 decades at the 7nm node.
The Ge-Sb-Se-N (GSSN) selector is one of the best materials reported by CEA-Leti. It supports extremely low leakage current, and electrical characteristics can be controlled by changing the percentage of antimony, nitrogen doping conditions, and annealing temperatures.
In the past annealing temperatures for selector materials as high as 400 degrees have been cited. Weebit-Nano claim the stack processing will have no FEOL consequences, so it must be assumed that they have reduced or removed any need for high-temperature annealing, meaning that their SiO memory will not suffer the effects which have to date limited ferroelectric memory progress. (See my earlier post on another low-temperature technology.) This might imply the use of a new selector composition.
Quantitative data to support their claims is thin on the ground. Write endurance in the range of 10⁵ to 10⁷ cycles is claimed. A “low operating voltage” is also claimed.
Modelling the Cell
While Weebit-Nano did provide I/V characteristic curves for the memory cell, the curves lack the essential numerical data, they are shown in the figure below on the left.
Nonetheless, I decided to use Weebit’s curves to try to back out the behaviours of the memory element and selector.
I can start with a simple assumption: A new memory must be voltage compatible with other 3Volt components and other circuit blocks. To meet this requirement, Weebit-Nano and Leti will have needed to develop versions of the SiO memory and selector with threshold voltages of about 1Volt and conducting currents of ~1 x 10⁻⁴ Amps.
The right-side curve above shows the extracted I-V characteristics of a selector which would match the characteristics required of a ~1Volt threshold voltage SiO memory element, while maintaining 3Volt system compatibility and a reasonable read current discrimination ratio.
For illustrative purposes the figure below is an estimate of the forward and reverse I-V characteristics of a suitable memory element again as a best extraction from the Weebit-Nano supplied I-V plot. The green line represents its low-resistance state (SET), and the purple its high resistance state (RESET).
The yellow arrows in these extracted memory characteristics indicate the width of the read window and correspond to the space between the two switching transition lines in the Weebit-Nano plot in the earlier figure.
In the following figure I have superimposed the I-V characteristics (red) of the selector on those of the memory element, when the memory element in its low resistance state (green/RESET), to determine the interaction between the two. This approach represents the two terminal characteristics of memory stack, with the selector acting like a series resistance load for the memory. As would be the case for a resistor, the I-V characteristic curve for the selector is reversed, with one terminal of each device anchored at the applied voltage. The intersection of the two curves then determines the series current of the stack.
The yellow arrows mark the voltage width of the read window and the switching current. The black and red dots mark the current switching transition.
In this case, the selector’s curve is illustrated at the extreme left side of the read window. When the voltage applied to the stack becomes high enough to overcome the selector’s threshold voltage the selector will switch to a higher current, as is required to read the memory in its low-resistance state. While, in this example, the selector is shown at the lower voltage side of the read window, more normal operation would be at the midpoint of the read window. When the selector switches, the stack’s current will immediately rise to the point at which the selector’s ON current matches the current in the low-resistance memory element, indicated by the red dot.
I should mention that the selector’s threshold switching current is an important switching parameter. In fact, in the design of a stack one tries to keep the selector’s leakage current at switching higher than that of the memory element, so that the selector switches first. If you look at the memory element’s switching characteristics in its low resistance state, switching actually occurs when the selector’s current equals the memory element’s leakage current. That current defines one side of the memory window.
In the next figure the selector is now superimposed on the characteristics of the memory element in its high resistance state (purple/RESET). The voltage applied to the stack is at a value just at the upper limit of the read window. Above that voltage switching would occur. The black dot indicates the more normal read window mid-point operation. Normally, when reading the memory in its high resistance state the selector does not switch and therefore no read current is detected, signifying the memory is in its high resistance state.
Any threshold switching of the selector would be undesirable, since the switching of the selector puts the red dot at a level that will drive the memory element to its low-resistance state, so this defines the extreme of the upper read window. When writing the memory switching does occur, driving the memory element to its low resistance state. Both devices in the stack switch in cascade fashion, first the selector followed by the memory element.
The Issue of Forming
I understand from Weebit-Nano that to ensure Forming is carried under exactly the same conditions for all memory cells in the 128kbit memory array module, Forming will be part of the normal memory test procedure before customers receive the arrays.
With this step, unlike many who have gone before, Weebit-Nano appear to recognize that controlling the precise conditions under which the filaments are Formed, for both of the devices in the stack, is important in guaranteeing reproducibility, reliability and device performance.
It is not clear how Forming will be dealt with in high bit density arrays and SoC ICs, when the SiO memory module is monolithically integrated and interfaces directly with other circuit elements. In these cases test time and cost might become an unacceptable burden. GSSN selector materials have a negative temperature coefficient of Forming, therefore the Forming voltage could be reduced through the use of a hot plate-based Form and test method.
The Role of the Scavenger Film
What is described by Weebit-Nano as an “oxide vacancies enhancement” (OVE) film is an important and key feature of their SiO memory structure. Its presence answers a key question: If you are going to build a conducting filament consisting of just oxygen vacancies what and where is the source?
The series of illustrations in Figure 3 provide a brief and simplified history of the evolution of the SiO-based ReRAMs. The starting point (a) utilises the fact that SiO films, especially the sub oxides, are a good source of oxygen vacancies. It is possible to create a conducting filament, and even a primitive memory of sorts, from that source alone.
The next step (b) was the recognition that SiO-metal interfaces are a natural source of oxygen vacancies and it is possible by electromigration to build or Form a permanent filament of electrode material (green) in the manner of an anti-fuze or a string of silicon inclusions. Then, at a small gap close to one electrode surface, where there is a more generous supply of oxygen vacancies, a more reliable form of memory switching becomes possible. This gap is outlined by the red dashed lines in the figures.
If the requirement is to build the complete filament of oxygen vacancies, then some means of oxygen vacancy enhancement is required. For the Weebit-Nano memory device (c), at the Ti-SiO interface the Titanium electrode becomes an aggressive oxygen scavenger and provides the required level of oxygen vacancy enhancement and a generous supply of oxygen vacancies.
That final step is the reason why the term “oxide vacancies enhancement” is used to describe the role of the Ti. Leti used Ti for their work on similar HfO memory stacks. Others have used Ta and silicon. Almost all metal and semiconductors interfacing with oxides offer enhancement or a source of oxygen vacancies: as the metal becomes more active, its role moves from enhancement to that of an aggressive scavenger.
The secret is to find a metal that can provide an abundant supply of oxygen vacancies without either detracting from any of the memory characteristics, or resulting in unintended resistance changes. For ReRAMs over the years, and from the contributions of many different researchers, the more complete understanding of the metal-oxide interface and oxygen vacancies has been a success story that is leading us to an understanding equal to that of single crystal solid state materials and devices, and (it is hoped) more reliable NV memory.
Although the shape of the vacancy filament has not been disclosed, any narrowing is likely to be the location of the switching for the formed memory, and this narrowing is possibly close to the other electrode interface. It is unlikely that the complete oxygen vacancy filament is switched between the LRS and HRS.
One interpretation of the operation of an SiO memory can be found in the animation in another Memory Guy post.
The next three figures summarize the fabrication and Forming options that I think might have implications on scaling. They illustrate three alternatives for oxygen scavenging by the titanium to create a conducting filament of oxygen vacancies. My question is: Which one is the most likely representative of the real situation, and will it have scaling implications? I also wonder about the location of resistance changes. Knowledge of the diameter of the conducting filament would be helpful in such an evaluation. At this time the ability to provide truly accurate answers to those questions would enhance the probability of Weebit-Nano’s success.
Please comment on this section if you have something to share.
If the company’s predictions of scaling to the 7nm node with a 4f² cell size can be achieved, then conducting filaments of the order 3 to 7nm diameter will be necessary. How might they be formed?
I will present three possible options.
The first of these figures illustrates the situation where during fabrication the reaction between the two films at the Ti-SiO interface creates a layer of oxygen-rich material (coloured pink) and, more importantly, a reservoir of oxygen vacancies. The vacancies are then moved and used to build the Formed column and bridge the inter-electrode gap. (The question marks above would represent the minimum cell size, and the arrows below indicate the filament diameter.)
The second figure would be the situation where the reaction between the Ti and SiO. and the generation of vacancies, occurs at the time of Forming and is local and equal to the diameter of the filament.
The third figure is again the situation where the creation of the oxygen vacancies occurs at the time of Forming, and the resistance of the by-product of oxygen scavenging causes the Forming current to move to its edge as the filament grows.
In the extreme there is a factor of 10⁶ difference in resistivity between TiO and Ti. Since the titanium is scavenging oxygen to create a reservoir of the oxygen vacancies that it can use to build the filament, then it would naturally follow that there will be a film of insulating, or partially insulating, TiO at one end of the filament.
If such an insulating region at the SiO-Ti interface is created during Forming, and remains fixed and stable, it would eliminate the possibility that the switching is some type of SiO-Ti interface effect. Until evidence to the contrary is provided, for the moment that cannot be ruled out. A stable interface would also mean that the location of the structural changes responsible for the memory resistance are situated well away from the SiO -Ti interface.
If the first and third of these figures represent the real situation, with respect to the formation of a reliable and repeatable filament, then there are implications for scaling predictions, highlighted with the red arrows.
Weebit-Nano have recruited an impressive array of talented and experienced people as the technical and management team. If that alone would be a guarantee of success then its job done, or, as horse lovers would say: “Home and hosed”. However, for them (and they will know) the availability of commercial competitive Weebit-Nano SiO-based or OxRAM memory products, from a large and reliable source of silicon and design-in wins, will be the real measure of success.
 Reliability and Variability of 1S1R OxRAM-OTS for High Density Crossbar Integration, D. Alfaro Robayo, et al, Proc IEDM 2019.
 Optimized reading window for Crossbar Arrays thanks to Ge-SE-Sb-N based OTS Selectors, A. Verdy et al, Proc IEDM 2018.
 Video: The Inner Workings of SiO ReRAM, Charlotte Streeter, Ron Neale
12 thoughts on “Weebit-Nano’s First Small Steps on the NV Memory Road”
Frederick Chen wrote a comment on LinkedIn that you might want to address here:
“It’s not clear how they deal with current compliance.”
“The maximum current looks flat in Weebit’s original curves. It appeared to be a transistor-set compliance rather than a resistor-set compliance.”
“The latter would be more reasonable for the crosspoint but would be an extra load for RESET.”
Mind answering him here on The Memory Guy?
The current scale of that figure was logarithmic and ranged over 5 or 6 decades and, pictorially at the top end, values of resistors tend to look flat. More likely than not, the characteristics are for a memory stack in isolation and made on instrumentation where the compliance current can be set and fixed.
If you examine the I-V characteristics of a modern scaled threshold switch/selector you will first notice the absence of a negative resistance snap-back. It is still there but hidden from a two terminal viewpoint. The reason is series resistance – if you then examine the conducting state characteristics you will find they represent those of a constant voltage device in series with a resistor. Also remember the Memory is in its Formed state and only a small region of the filament is switching, the rest is series resistance. The unavoidable presence of that resistance for both devices in a scaled memory stack does provide a degree of self-compliance.
Weebit-Nano have released for production a monolithic chip design. That would suggest to me as well as layout that would at least include some degree of circuit simulation. There is enough memory talent in that company to appreciate and to deal with any possible problems of the type you mention, if not, to put it mildly they would have been very negligent.
While we were provided with a very comprehensive off-the-record briefing which provided us with enough detail to suggested Weebit-Nano might know what they are doing, and made it worth spending our time writing about them, it did not provide the propriety details of the driver and decoders circuits of the memory matrix. So I am unable to provide you with the details of how any possible need for current compliance has been dealt with.
Thanks Ron, for your reply. looking at the RESET-SET I-V again just now, it looks like the read operation is different for negative and positive directions. Looks like positive gives the better ratio.
Frederick. If you mean the single Weebit-Nano supplied set/reset curve there could be a difference and that small difference might be expected as a result of contact effects, or if as I mentioned as a result of scavenging there is a more resistive interface layer of TiO at the SiO-Ti interface that could again could exhibit some contact effect which might show up as a difference. If you are referring to my extracted curves then the difference is more likely to do with my extraction methodology. Clearly if in reality there is a difference, then use the best one. My question to you would be, does it matter ? I think it is unlikely in the context of a digital memory array reading would be in both directions. It might be relevant in some type of analogue or MLC application for the memory.
May I share with you some background. Off-the-record Weebit-Nano did provide us with the complete quantitative details of the I-V memory characteristics for their SiO devices. Because of that obligation, I had to extract my published version of the I-V characteristics from the public domain information. With of course the application of what in my view would be the present day electronics required voltage and current boundary conditions.
Ron, thank you for that great detailed review of the WBT technology.
I don’t know whether you have come across them, but there is another RERAM player (this one is non-filamentary) being funded via an Australian public listing – 4DS Memory.
4DS is more directly focused on Storage Class Memory and appears well down the track, having partnerships with both Western Digital and imec.
I’m just wondering whether you have had reason to review this alternate approach?
Allan. As a result of some background exchanges, you will find a question was raised with respect to 4DS in relation to one of my articles which was published at an earlier date here on on The Memory Guy website (https://thememoryguy.com/ceram-moves-front-and-center-on-the-nv-memory-stage/#more-2797) for which I provided an answer. To answer your present question it needs something more than arm waving, company name dropping and vague PR claims for something to land on my desk suggesting that an article might be possible. My most recent notes on 4DS indicate some wafers passing through Imec and not much else since. What is needed is some quantitative detail on what has been achieved by 4DS or their partners and what “ well down the track” actually means. I think Weebit-Nano also have some storage class memory application or large scale memory application as target area of application, with the year 2024 as the date. So to answer your question at the moment I have no reason to review 4DS.
Thanks for the frank response, Ron. More than a few share your thoughts on this subject. If any collective efforts on sourcing deeper information have any success, I will highlight accordingly.
Hi Ron, I thought your readers might be interested to know that Weebit Nano is continuing to take steps (and some leaps!) forward on the NVM road. Together with our development partner CEA-Leti, we have now produced, tested and characterized fully functional 1 Mb ReRAM arrays in 28nm FDSOI on 300mm wafers. To date the test results support all our claims of robustness, endurance, and data retention for our 28nm arrays. An essential step as we bring Weebit’s ReRAM toward production status. You will find further information on our website: https://www.weebit-nano.com/press.
Thanks Eran. As well as embedded, now what appears to be an important step in your company’s other memory product target area has been made. Combining your memory with SOI will I am sure heighten the interest of those with responsibilities and interests in the radiation hardness.
Historically at the higher lithographic nodes it is known that the threshold switch is radiation hard in all environments at strategic and space levels, the SiO OxRAM memory element is likely to be its equal.
Although it will be interesting to see how a vacancy dependent memory performs when subjected to a displacement damage radiation environment, such as cosmic radiation and neutrons, where a few new vacancies are likely to be created.
So the combination of inherently rad hard memory stack with SOI, the latter to deal any silicon problems and you might find you have produced the World’s most radiation tolerant memory. If so I think you might find that those with responsibility for maintaining strategic level and space radiation hard component capability might soon be knocking at your door, if not they should be.
When I raised questions with you about radiation hardness I was informed test were underway. I understand there is a new program underway to evaluate the radiation hardness of MRAM I think samples of Weeebit-Nano’s new OxRAM -SOI should be included. At the highest radiation levels the comparative results will be extremely interesting.
Update 25th January 2022 Weebit-Nano have just announced completion of an important and essential next step on one of their two paths towards persistent and embedded memory products. They report the fabrication of arrays of their 1S1R stacked memory cell structure, that is the thin film matrix isolation selector device and memory in the form of 1 kilobit 32 x 32 bits arrays. These new arrays are fabricated in 130nm technology and include the minimum necessary associated driver and decoder circuits.
Late last year Weebit-Nano announced they had received from manufacturing the first silicon wafers that integrate their embedded Resistive Random-Access Memory 128kbit (ReRAM) module inside complete subsystem demonstration chips. Against that, the most recent announcement of kilobit arrays might appear a backward step. Not so, the 1T1R memory structure used in the 128kbit module has as its target embedded applications of all types for a variety of different customers. The 1S1R stack and crossbar array, highlighted in this latest accomplishment has large discrete memory arrays and multiple stack products as a longer-term target.
Comments are closed.