What is a 3D NAND?

Applied Materials' Explanation of 3D NANDIn the prior post we discussed the need to go vertically into the body of the die, since NAND flash can not be scaled much farther in length and width on the die’s surface.  Toshiba invented a 3D NAND which has been adopted and refined by all flash makers.  The idea is simple: Rather than shrink the cell’s length and width, why not turn the NAND string so that it’s standing on its end?

This concept is illustrated by this post’s first graphic, which was provided by Applied Materials.  (Click on the graphic to see the whole thing at a larger size.)  A standard NAND string that normally runs longitudinally is turned on its end to become a vertical string.  Not only that, but it makes things easier if the string is split into two sections and formed into a “U” shape rather than a single column.

Naturally this can’t be done by manufacturing NAND strings and folding them.  Instead the string is formed vertically using a completely different manufacturing process than is used for standard NAND flash.  In fact, this is a technique that is new to all of semiconductors.

If you can lay down a horizontal series of control gates, then run a vertical series of floating gates and a channel that responds to those gates, then you can build strings that may be several cells long in the same area as a single planar cell.

How Vertical NAND Compares Against Planar ProcessesHow much space does this save?  A sixteen-cell deep string effectively shrinks the production process to ¼ its size, as is shown in a top-down view in the second illustration.  (Click on it to enlarge.) This is a very abstract representation of sixteen NAND flash cells which are not necessarily in the same string.

Here’s what the diagram represents: At a half pitch of 40nm (making the cell 80nm on a side) a block of sixteen planar memory cells would consume a certain amount of space.  When these 16 cells are manufactured vertically they would consume as much area as a single one of those 16 planar cells.

What would it take to fit 16 cells into the same area using a planar process?  The third part of the diagram shows us this – the process would have to shrink to a half pitch of 10nm, or ¼ that of the first block.  That’s a significant jump equivalent to about four process generations!

For vertical strings of different lengths this ratio would be different, in fact it is the square root of the number of cells in the string, so a trench 4-cells deep would provide as many cells in a given die area as a planar process with half the pitch, and a 64-deep trench would rival a process with one eighth the pitch of the 3D approach.

Another way to put this is that if you were to draw a diagram like the second graphic that had 64 boxes representing planar cells (in an 8×8 grid) then each box would have to be 10x10nm in order for the whole set of 64 boxes to have same 80x80nm size as the 40nm trench box.

So here’s how these different numbers of trenches compare against their planar counterparts:

  • 16-cell trenches at 40nm compete against 10nm planar cells
  • 32-cell trenches at 40nm compete against 7nm planar cells
  • 64-cell trenches at 40nm compete against 5nm planar cells
  • 128-cell trenches at 40nm compete against 3.5nm planar cells

By shifting from planar 2D NAND to a 3D technology the pressure is instantly removed from lithographic scaling.  Cost reduction is no longer solely determined by shrinking the horizontal patterns on the surface of the chip.  Instead it becomes a factor of how many transistors you can make in a single vertical string.

The next post will get into the mechanics of how such vertical strings can be manufactured.

Above I mention a sixteen-bit string, but that’s just something that The Memory Guy chose for convenience’s sake.  NAND producers are already talking about making vertical strings 128 cells high, which, with the “U” shape in the diagram yields a 256-cell string.  It is fathomable that they could go well beyond this level, but nobody’s yet publicly disclosing their research efforts in this direction.

How many levels can be used by this kind of approach?  Today memory makers argue that, without scaling the process, it takes twice as many layers to double the chip’s capacity in the same die area, and that going from 128 layers to 256 might be impossible.  That may well be the case, but I would not be surprised to see them abandon binary string lengths moving to strings of perhaps 179 cells, or other peculiar numbers, as they work to optimize the cost per gigabyte.

Let’s be perfectly clear, though: 3D NAND is not stacks of chips.  A lot of people mistakenly think this is the case.  The cost of a semiconductors is roughly proportional to its die area.  A stack of eight chips is over eight times as expensive as an individual chip of the same area as the stack.  Stacking chips doesn’t save money.

The trick to Moore’s Law is to continually shrink a given function so that its price will decline.  This is the economic basis of the semiconductor market, and it would fall apart if chips stopped shrinking, or if prices stopped declining.

By going vertical, NAND flash makers are finding a way to get more bits onto a chip of a given size than they can through simple lithographic shrinks, increasing the number of bits per chip, even if they aren’t able to shrink the length and width of a cell on that chip.

This post is a part of a series called What is 3D NAND? Why do we need it? How do they make it? that was published in weekly segments during the fourth quarter of 2013 on The Memory Guy blog.  The different sections are listed below, with a hot link to each section.

Click on any of the above links to learn more about 3D NAND technology.

9 thoughts on “What is a 3D NAND?”

  1. Usually in the 2D flash memory we see NPN junction near each one of the memory cells done by doping. How can doping possible in a vertical channel ? are they doing this NPN at all ?

    1. Jacob, I had the same question, so I asked the books’ author, Betty Prince.

      She says that none of the vertical junctions are doped. It would be very difficult.

      Junctionless channels are possible because, for a Gate-All-Around nanowire memory device, the side fringing field from the gate induces an inversion in the source/drain region which makes the device work without doping.

      There has been further work in this area for even smaller nanowires which involves a bulk effect pinch-off effect under the gate which turns the device on and off. Much work is ongoing in this area.

      This is covered in Chapter 3 Section 4 of her book. In particular see figure 3.26.


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