Why 3D NAND is Stuck at 40nm

Top-Down look at a 3D NAND column with its concentric rings of materialsI recently was asked how much 3D NAND pitches had shrunk since the technology’s 2013 introduction.  Samsung made a big to-do about using 40nm back in 2015, but the company and its competitors don’t seem to have given an update since then.  Shouldn’t it have gone to smaller processes like 35nm, 25nm, 20nm, etc.?

The Memory Guy’s reply was that it’s nearly impossible to shrink the pitch of 3D NAND, at least not much.  This is because of the way that it’s made.  I’ll use the original Toshiba BiCS structure as an example since it’s simpler than most processes.  To help you visualize the process this post’s graphic is a conceptual drawing of one of the 3D NAND’s vertical strings viewed from the top.

Here’s how vertical 3D NAND flash strings are manufactured:

  1. Etch deep narrow holes through all of the 3D NAND’s layers. Today these holes have aspect ratios of about 60:1 which is remarkable. Think of a 1” dowel (2.5 cm) that’s 5 feet long (60”, or 1.5 meters), these holes are like that, with almost perfectly parallel walls all the way from top to bottom.
  2. Precisely coat the sides of this deep narrow hole with 5 layers of material:
    1. First with a very thin layer of silicon dioxide (SiO2) accurately from top to bottom, making the hole narrower.  This is shown as pale blue in the diagram above, and serves as the gate oxide.
    2. Then coat that with a very thin layer of silicon nitride (Si3N4), accurately from top to bottom, making the hole even narrower.  This is the charge trapping layer and is shown in yellow.
    3. Then coat that with another very thin (blue) layer of SiO2, accurately from top to bottom, making the hole still narrower.
    4. Then coat that with a very thin layer of conductive polysilicon, accurately from top to bottom, making the hole still narrower.  This layer is shown in red, and serves as the channel.
    5. Finally, fill what’s left, which by now is a very tiny hole, with SiO2 (blue).  This, too, must be uniform from top to bottom or the whole string will fail to work!  This final insulating fill helps to thin the channel which makes it behave better.

So the thickness of the layers that line the hole determines the minimum diameter of the hole, and that sets how tightly the holes can be packed.

And the thickness of the layers is about as small as they can be made. They are only a few atoms thick.

The photo below, from ChipWorks (now a part of TechInsights) is an actual photograph of the layers that the diagram at the top of the post is intended to represent.  It’s an Intel-Micron floating gate 3D NAND from 2015.  My associate Andy Walker added the annotations of the different materials in the layers.

TEM top-down shot of the pillar in a 3D NAND

It’s a lot more complex than the first example.

Look closely at that second layer from the bottom, which is pure silicon.  Those patterned dots are individual atoms.  The thicknesses of each of the layers has been carefully considered for how it interacts with the other layers, for how electrons will behave across that layer’s thickness, and for how manufacturable a layer of that thickness will be.

All of this means that 3D NAND should remain at 40nm for the foreseeable future. Pitch scaling is rarely considered any longer in NAND.  Now R&D is focused on layer count, logic-under-array, and improved staircase configurations.

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14 thoughts on “Why 3D NAND is Stuck at 40nm”

  1. Hi Jim,

    If you take the equivalent of planar NAND pitch, which was the word line pitch, then the equivalent 3D NAND pitch is the total thickness of the horizontal word line layer and the insulating layer between the word lines, which is shrinking as the number of layers increases.

    The industry seems to have changed the pitch definition for 3D NAND from the vertical word lines to the bitline pitch, not unusual as technologies evolve:)

    1. Yes, that’s a point didn’t include.

      If you look at the amusing slide that Jeongdong Choe presents with skyscrapers made of 3D NAND stacks, it’s very clear that the layer thickness is shrinking pretty fast.

      I would guess that the motivator if this is to keep the aspect ratio of the holes manageable. I would slso suspect that it makes it a little harder to qualify QLC every time the thickness is scaled.


  2. The pitch of the memory hole determines the smallest 1/2 pitch of 3D NAND.
    Although the pitch of the memory hole is about 155nm-160nm. However, the memory hole is designed in a staggered arrangement. This requires two metal bit lines for one memory hole pitch.
    This means that the pitch of the metal bit line is 1/2 of the memory hole pitch (77.5nm~80nm).
    For this reason, as long as the pitch of the memory hole cannot be reduced, 3D NAND is stuck at 40nm.

    1. Another pitch consideration is that the bitline litho would have to go from double patterning to quad patterning to push far below 40 nm.

      1. Dick,

        Good point, but would they be able to deposit all the layers they need into smaller holes?

        You understand process much, much better than I do. I appreciate your weighing in on this!


  3. Hi Jim

    Thanks for the article on this issue!

    Any idea whether Samsung has changed the process in its V-NAND? Gen1 and Gen2 MLC V-NAND was on a 40nm process. Since then they haven’t given out any data on what node they are using.

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