Why Do We Need 3D NAND?

NAND Flash Capped Gate StructureA memory chip of a certain area costs about the same amount to produce, no matter how many bits it holds. Naturally, the more bits you can cram onto this chip, the cheaper the price per bit will be. Low cost is of the utmost importance in the world of memory.

Memory chip makers have shrunk the cost of a bit some nine orders of magnitude since the 1960s largely by shrinking the process, or “scaling” to increasingly tighter process geometries.

Flash has always been expected to reach a scaling limit. Over the past few generations technologists have developed new processes and have harnessed innovative materials to push scaling farther than it has gone before, but today we are approaching the point at which planar NAND just cannot any longer be shrunk.

The technology has progressed from the standard floating gate to a capped structure (pictured in this post’s graphic), since the constant shrinks have caused the undesirable capacitive coupling between the floating gates of adjacent cells to rival the desirable coupling between the control gate and the floating gate.

The capped cell was developed to solve this problem, but capped cells can only be shrunk to about 20nm, since the capping material limits how closely floating gates can be placed to one another.

To get past this some manufacturers have replaced the silicon-based gate dielectric (aka blocking dielectric – the dielectric between the control gate and the floating gate) with a high-k material that allows the two gates to be placed closer to each other while still maintaining a high enough desirable capacitance to do the trick.

Even this provides only a little more shrinkability. What happens after that?

In 2007 Toshiba presented a novel idea to move NAND even farther. Rather than try to continue shrinking the cell’s length and width, why not turn the NAND string on its side?

The way this is done will be covered in the following post.

This post is a part of a series called What is 3D NAND? Why do we need it? How do they make it? that was published in weekly segments during the fourth quarter of 2013 on The Memory Guy blog.  The different sections are listed below, with a hot link to each section.

Click on any of the above links to learn more about 3D NAND technology.

12 thoughts on “Why Do We Need 3D NAND?”

  1. Hi JimHandy,

    The materials in your blog are really valuable to people who working in semi area, and I learned a lot from your blog in the case of flash knowledge.

    And I would like to consult you a quesion, in the case of planar NAND flash, there is source and drain for each unit cell, so how about 3D NAND flash, it looks like no any source and drain any more for each unit cell, is it right?


    1. Jun Fang,

      Thanks for the compliment!

      I will double-check with people who understand this better than I do, but I believe that there is no source or drain for most of the transistors in a planar NAND string. You might think of it more as a single transistor with 64 gates, all in a row.

      I’ll double-check, though, in case I am wrong.


      1. OK, I was wrong about that!

        Planar NAND has source and drain implants, but 3D NAND does not.

        I don’t really understand why, but I am told that undoped thin film transistors don’t need the implant because they are based upon a different kind of MOSFET.

        You’re going to have to talk to someone smarter than me to find out more, I’m afraid!


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