Why ST-MRAMs Need Specialized DDR3 Controllers

Everspin ST-MRAM press photoEverspin and Northwest Logic have just announced full interoperability between Northwest Logic’s MRAM Controller Core and Everspin Technologies’ ST-MRAM (Spin-Torque Magnetic RAM) chips. This interoperability is hardware proven on a Xilinx Virtex-7 FPGA and is now available for designs needing low-latency, high memory throughput using MRAM technology.

Since The Memory Guy knew that Everspin’s EMD3D064M ST-MRAM was fully DDR3 compatible, I had to wonder why the part would require a special controller – couldn’t it simply be controlled by any DDR3 controller?

Everspin’s product marketing director, Joe O’Hare, took the time to explain why a modification was necessary:

  • The Everspin DDR3 MRAM has a significantly lower density than a DRAM..  At 64Mb it is 1/500th the density of a 1Gb DRAM.  This presents certain issues with some DDR3 controllers.
  • The MRAM uses a small page size compared to a DRAM.  DRAMs handle refresh better (at the expense of power) by having a very large page, since every page access results in a refresh of the entire page.  Since it’s not a dynamic memory (and is, in fact, nonvolatile) Everspin’s MRAM doesn’t need to be refreshed, so it has been designed with a greater focus on power and speed, partly by using a smaller page size.  The page size is sufficiently small that most standard DDR3 controllers don’t automatically accommodate it.
  • In addition there are various differences between the MRAM’s activate and row address timing and those of a typical DDR3 DRAM.  Standard DDR3 controllers don’t offer a broad enough range of options to accommodate Everspin’s MRAM.  The parameters of Northwest’s controller have now been set up to accommodate both the DRAM timing and that of the MRAM.

With this in mind it’s pretty obvious why a special controller is necessary.  Designers probably wouldn’t expect these differences to get in the way, but since standard DDR3 controllers have been specified to work with a relatively narrow range of parts (as DRAMs tend to be)  it took an extra effort to bring them into compatibility with the new ST-MRAM.

My congratulations to Everspin for recognizing this issue, and for working to provide the required support.