This product appears to be a variation on the Hybrid Memory Cube, or HMC concept detailed in a prior post.
Remember that the HMC stacks a number of DRAM chips atop a logic chip. The memories store data and communicate to the logic chip through thousands of through-silicon vias (TSVs) while the logic chip handles communications with the outside world.
The ST/CEA chip, designed with help from Cadence Design Automation, takes the technology one step further, coupling the high-bandwidth DRAM interface with logic chips that have real processing power. While communications based on a Network on a Chip (NoC) communicate within either of the logic chips at a rate of 550 million transfers per second, communications between chips in this package still keep up a respectable rate of 200 million transfers per second.
Readers who want to know more about NoC architecture can download a free white paper from Objective Analysis: NoC Interconnect Improves SoC Economics. Those who would like to learn in-depth technical detail about the WIOMING project are directed to an excellent EDA360 Insider blog post by Steve Leibson of Cadence.
The companies have created a “proof of concept” prototype named WIOMING that, according to the companies, provides 12.8GBytes/s of memory bandwidth, or 50% more than today’s most advanced 533MHz dual channel LPDDR2 solutions, at 20 percent less power. In the near future the companies expect to create designs that deliver more than 34GBytes/s to deliver high-performance graphics in smartphones and tablets.