DRAM – Page 4 – The Memory Guy

Valuable Memory Technical Resources

Ever since moving to Silicon Valley some time ago The Memory Guy has worked with a number of impressively-talented engineers from India. Some are educated in the US, while others are educated in India. One university that produces excellent engineers is the Indian Institute of Technology, or IIT.

It comes as no surprise, then, to find a valuable resource produced by an IIT faculty member. Dr. Sparsh Mittal, an assistant professor at IIT Hyderabad, reached out to me to share some papers that he thought might be of interest to Memory Guy readers. They were a few of roughly 40 papers that he has posted on his publications page. He explained that he previously worked at Oak Ridge National Lab, in the US.

Dr. Sparsh has published several very comprehensive surveys on memory systems, both conventional and emerging, covering topics like DRAM reliability, NVM/Flash, ReRAM-based processing-in-memory, and the architecture of neural networks. The web page lists 34 surveys, eight of them Continue reading “Valuable Memory Technical Resources”

Memory Market Falling, as Predicted

It’s earnings call season, and we have heard of a slowing DRAM market and NAND flash price declines from Micron, SK hynix, Intel, and now Samsung. DRAM prices have stopped increasing, and that can be viewed as a precursor to a price decline.

Samsung’s 31 October, 2018 3Q18 earnings call vindicated Objective Analysis‘ forecast for a 2H18 downturn in memories that will take the rest of the semiconductor market with it.

Those familiar with our forecast know that for a few years we have been predicting a downturn in the second half of this year as NAND flash prices fall, followed by a DRAM price collapse. After the DRAM collapse the rest of the semiconductor market will undergo a downturn.

We’ve been calling for this downturn for some time. Dan Hutcheson at VLSI Research has been videotaping our forecast every December for the past Continue reading “Memory Market Falling, as Predicted”

Why DRAM is Threatened by SSDs

Conventional wisdom holds that SSDs will someday displace all HDDs, but in reality SSDs are proving to be more of a challenge to the DRAM market than to the HDD market.

Right now you are probably reviewing the date of this post to make sure it’s not dated April 1. I assure you that this is the truth. To understand it, though, you must look at a computer as a computer architect would, or, in other words, the way that an application program sees the memory/storage hierarchy.

To the application program there is no HDD and memory, there is only memory. The Virtual Memory system, a part of the operating system, hides the difference between the two by moving code and data into DRAM as it is needed and back onto the HDD when it is no longer important, without telling the application program that it is moving anything around. I like to tell people that the DRAM makes the HDD look fast, and the HDD makes the DRAM look big.

If you think of the DRAM as something that makes the HDD look fast, then additional DRAM should help to make the Continue reading “Why DRAM is Threatened by SSDs”

How to Worsen a DRAM Shortage

In an interesting twist to today’s ongoing DRAM shortage, the Fuzhou Intermediate People’s Court, Fujian Province, China today granted a preliminary injunction to prevent Micron’s Chinese subsidiaries from manufacturing, selling, or importing certain DRAM modules and solid state drives in China.

This injunction, according to a Micron press release, was filed without allowing Micron to present its defense, a process which Micron finds to be: “inconsistent with providing a fair hearing through appropriate legal processes and procedures.”

Micron’s customers in China will find that the DRAM shortage has just become even worse than it already was. Before today China’s government was concerned enough about the shortage’s rising DRAM prices to have launched a price fixing investigation only one month ago. One result of today’s decision will be that there will be less DRAM in China, and that will probably cause prices to rise even more.

What will be the impact to Micron? I find it unlikely that this injunction is likely to change any DRAM maker’s business much during a shortage. Any lack of Micron DRAM in China is likely to be serviced by Samsung and SK hynix, but since there’s a shortage, these companies will need to reduce their shipments outside of China to satisfy Continue reading “How to Worsen a DRAM Shortage”

Storage/Memory Hierarchy 40 Years Ago

Last year I stumbled upon something on the Internet that I thought would be fun to share. It’s the picture on the left from a 1978 book by Laurence Allman: Memory Design Microcomputers to Mainframes. The picture’s not too clear, but it is a predecessor to a graphic of the memory/storage hierarchy that The Memory Guy often uses to explain how various elements (HDD, SSD, DRAM) fit together.

On the horizontal axis is Access Time, which the storage community calls latency. The vertical axis shows cost per bit. The chart uses a log-log format: both the X and Y axes are in orders of magnitude. This allows a straight line to be drawn through the points that represent the various technologies, and prevent most of the technologies from being squeezed into the bottom left corner of the chart.

What I find fascinating about this graphic is not only the technologies that it includes but also the way that it’s presented. First, let’s talk about the technologies.

At the very top we have RAM: “TTL, ECL, and fast MOS static types.” TTL and ECL, technologies that are seldom Continue reading “Storage/Memory Hierarchy 40 Years Ago”

Wafer Shortages and DRAM/NAND

Recently I have been hearing concerns that an impending wafer shortage might drive today’s DRAM and NAND flash shortages to epic proportions.

The Memory Guy doesn’t pretend to have any understanding of the raw wafer business, so I decided to consult Mark Thirsk, managing partner of Linx Consulting. Mark has been in this industry for quite a while and has a very good understanding of the ongoing status of the semiconductor materials supply chain.

Mark and I were on a panel together at SEMICON Korea in February, and he presented an interesting chart to compare the costs of different technologies. I asked him about this chart as well.

Here’s what Mark had to say:

“Our information is that major Continue reading “Wafer Shortages and DRAM/NAND”

Micron’s Super-Fast New 32GB NVDIMM

Micron Technology has introduced a 32GB NVDIMM-N. Perhaps the most important thing about this device is not so much its high density as the fact that it runs at higher bus speeds than competing NVDIMMs, doing 2933 megatransfers per second (MT/s), a speed that Micron representatives tell us is required to support Intel’s Skylake processor.

Up to this point NVDIMM-Ns have been limited to 2400 MT/s, which is fast enough for Broadwell, but which misses the mark for Skylake. Design is tricky even at this slower speed, requiring a number of expensive high-speed multiplexers in the DRAM’s critical speed path.

“Multiplexers?” Yes, NVDIMMs use them, even though no other kind of DIMM does. The Memory Guy can explain why, having just finished a report covering the NVDIMM market and technology.

Here’s a little refresher for those who either don’t remember or never knew that NVDIMM-N requires multiplexers. The NVDIMM-N looks to the system like a standard Continue reading “Micron’s Super-Fast New 32GB NVDIMM”

Super-Cooled DRAM for Big Power Savings

Recently Rambus announced that it was using cryogenic temperatures to boost computer performance in large datacenters. This research is being done in a joint project with Microsoft who is developing a processor based on Josephson Junctions.

This is an effort to provide a performance increases greater than can be attained through standard semiconductor scaling. The research project aims to attain improvements in cycle time, power consumption, and compute density, leading to better energy efficiency and cost of ownership (COO). The companies hope to gain side benefits of being able to squeeze more bits onto a DRAM chip thus reducing cost per bit, improving performance, and making DRAM chips less costly to produce.

The system these two companies are researching uses a memory system that is cooled to 77 degrees Kelvin (77°K) with a processor that operates at 4°K. To do this the memory system is bathed in liquid nitrogen while the processor is cooled by liquid helium. The temperatures are the boiling points of these two liquids.

Surprisingly, the fact that these two subsystems are in different Continue reading “Super-Cooled DRAM for Big Power Savings”

Using ECC to Reduce Power

A couple of papers at last week’s ISSCC (the IEEE International Solid-State Circuits Conference) caught The Memory Guy’s attention. Both SK hynix and Samsung showed low-power DRAM designs in which the refresh rate of the DRAM was reduced in order to cut power consumption, with ECC applied to correct the resulting bit errors.

Although I had not heard of this approach before, I have recently learned that researchers at Carnegie Mellon University and my alma mater Georgia Tech presented the idea in a paper delivered at another IEEE conference in 2015: The International Conference on Dependable Systems and Networks.

Here’s the basic concept: DRAM consumes most of its power performing refresh cycles, the issue for which it was given the “Dynamic” part of its name: Dynamic Random-Access Memory. This use of the word “Dynamic” is a euphemism. In reality the bits are constantly decaying, but that doesn’t sound as nice.

When the technology was developed in the early 1970s DRAM manufacturers offered to Continue reading “Using ECC to Reduce Power”

Is Intel Adding Yet Another Memory Layer?

At the International Solid State Circuits Conference (ISSCC) last week a new “Last Level Cache” was introduced by a DRAM company called “Piecemakers Technology,” along with Taiwan’s ITRI, and Intel.

The chip was designed with a focus on latency, rather than bandwidth. This is unusual for a DRAM.

Presenter Tah-Kang Joseph Ting explained that, although successive generations of DDR interfaces has increased DRAM sequential bandwidth by a couple of orders of magnitude, latency has been stuck at 30ns, and it hasn’t improved with the WideIO interface or the new TSV-based High Bandwidth Memory (HBM) or the Hybrid Memory Cube (HMC). Furthermore, there’s a much larger latency gap between the processor’s internal Level 3 cache and the system DRAM than there is between any adjacent cache levels. The researchers decided to design a product to fill this gap.

Many readers may be familiar with my bandwidth vs. cost chart that the Memory Guy has used to introduce SSDs and 3D XPoint memory. The gap that needs filling is Continue reading “Is Intel Adding Yet Another Memory Layer?”