Some recent news mentioned cMLC flash, which is short for “consumer MLC.” This term is used to differentiate between the cheapest available product, mainstream MLC, and products that are aimed at the computing segment, and thus carry higher price tags.
There are several of these higher-end products. Some have longer endurance, like eMLC and SLC flash. Some have faster interfaces, like ONFi and Toggle Mode. Then there are the combinations of these: a fast interface with enhanced reliability.
There are disadvantages to these. The consumer market Continue reading “What is cMLC Flash?”
Tessara’s Invensas subsidiary has announced a new packaging technology to produce what the company calls a “DIMM in a Package.”
The new product is said to deliver the capacity and performance of an SO-DIMM in a 16x16mm BGA. It is built using Invensas’ xFD technology.
I have seen examples of Invensas’ xFD and the first thought that struck me was: “Why didn’t I think of that?!?” It’s an elegantly simple approach to today’s connection conundrums. By staggering chips and mounting them face-down over holes for bonding wires the company connects DRAMs with far shorter interconnect lengths and less scrambling, leading to higher performance.
Although this technology is not yet covered in any of our current reports, we do have a report on cell phone packages: Flash Packaging: What Phone Makers Want and Why, that can be purchased for immediate download on the Objective Analysis website.
At a Conference in San Francisco today (Tuesday December 13 ) ST-Ericsson and CEA-Leti presented a paper on something the companies called a: “Breakthrough 3DIC with Wide I/O Interface.”
This product appears to be a variation on the Hybrid Memory Cube, or HMC concept detailed in a prior post.
Remember that the HMC stacks a number of DRAM chips atop a logic chip. The memories store data and communicate to the logic chip through thousands of through-silicon vias (TSVs) while the logic chip handles communications with the outside world. Continue reading “WIOMING: Another Spin on the Hybrid Memory Cube”
I got a phone call yesterday from Russell Fish of Venray Technology. He wanted to talk about how and why computer architecture is destined for a change.
I will disclose right up front that he and I were college classmates. Even so, I will do my best to give the unbiased viewpoint that my clients expect of me.
Russell is tormented by an affliction that troubles many of us in technology: We see the direction that technology is headed, then we consider what makes sense, and we can’t tolerate any conflicts between the two.
In Russell’s case, the problem is the memory/processor speed bottleneck.
Continue reading “A Change to Computing Architecture?”
In a December 1 press release IBM announced that the company will be manufacturing Micron Technology’s Hybrid Memory Cube (HMC) which IBM claims to be “the first commercial CMOS manufacturing technology to employ through-silicon vias (TSVs).”
This device is one that Altera, Intel, Micron, Open Silicon, Samsung, and Xilinx have all presented recently as a plausible solution to the difficulty of increasing the speed of DRAM/processor communications. The Hybrid Memory Cube Consortium (HMCC) website offers a deep dive into the details of the consortium and the technology.
Continue reading “IBM to Build Micron Hybrid Memory Cube”