3D NAND presents an interesting conundrum. To improve bit costs and continue along the path of Moore’s Law the layer count must increase. Unfortunately 3D NAND can’t benefit from lithographic scaling; it’s pretty much stuck at 40nm design rules forever. The natural way to reduce costs and increase chip density is by adding layers.
But adding layers increases the size of the staircase structure used to access the wordline layers.
With today’s structures, the addition of layers means adding stairs to the staircase – if you double the number of layers then the amount of die area required by the staircase doubles. At some point the staircase becomes so large that the die has fewer GB/mm² than a die with half as many layers.
An example of a staircase structure can be seen in the Continue reading “Solving 3D NAND’s Staircase Problem”
Recently I have been hearing concerns that an impending wafer shortage might drive today’s DRAM and NAND flash shortages to epic proportions.
The Memory Guy doesn’t pretend to have any understanding of the raw wafer business, so I decided to consult Mark Thirsk, managing partner of Linx Consulting. Mark has been in this industry for quite a while and has a very good understanding of the ongoing status of the semiconductor materials supply chain.
Mark and I were on a panel together at SEMICON Korea in February, and he presented an interesting chart to compare the costs of different technologies. I asked him about this chart as well.
Here’s what Mark had to say:
“Our information is that major Continue reading “Wafer Shortages and DRAM/NAND”
Chip reverse-engineering consultant Dick James pointed The Memory Guy to an absolutely amazing 25-second video of a 3D NAND chip. The video’s made by the Carl Zeiss company. It’s the second one from the top on this page: https://www.zeiss.com/semiconductor-manufacturing-technology/products-solutions/process-control-solutions/crossbeam-fib-sem.html
The video zooms around a portion of a 3D NAND die as layers are etched away and then restored. Only the tungsten parts of the chip are shown, with the rest appearing to be empty space. This serves to clarify it a good bit. Dick James says that this makes it the equivalent of a 3D x-ray tomograph.
It’s a promotional piece for a Zeiss tool called the “Crossbeam FIB-SEM” that can both image and mill a chip.
Now I doubt that most Memory Guy readers would have a need for this tool, nor be able to afford something which is doubtlessly very expensive, but I am sure that anyone would admire what it can do. I certainly find it to be impressive!
Naturally, Dick James was able to identify the chip just by looking at it. He says that it’s Samsung’s 32-layer part.
It came as a surprise to the Memory Guy on Monday to receive a press release from Micron indicating that Intel and Micron had decided to end their NAND flash partnership.
This agreement, which was begun in 2006, helped the two companies to aggressively ramp into the NAND flash market by combining their resources. NAND flash makers (as well as DRAM makers) need to make very substantial capital investments to participate in the market, and that’s not easy for a new entrant. Micron at that time was a very small NAND flash maker, and Intel wasn’t involved in the NAND flash market at all, so neither was in a position to succeed. By combining their resources the companies were able to become important contributors to the market.
The agreement initially appeared to be modeled after the very successful joint venture that Toshiba and SanDisk enjoyed. Each company would contribute half of the JV’s capital investment, and the same designs would be used to make both companies’ chips.
Over time Intel found itself in a familiar Continue reading “Micron and Intel to End NAND Flash JV”
Error Correction Codes, ECC, are not only important to today’s NAND flash market, but they have been a cause of concern to NAND users for a number of years. The Memory Guy has been intending for some time to write a low-level primer on ECC, and I am finally getting it done!
Why is ECC necessary on NAND flash, yet it’s not used for other memory technologies? The simple answer is that NAND’s purpose is to be the absolute cheapest memory on the market, and one way to achieve the lowest-possible cost is to relax the standards for data integrity — to allow bit errors every so often. This technique has been used for a long time in both communications channels and in hard disk drives. Data communication systems can transfer more data using less bandwidth and a weaker signal over longer distances if they use error correction to restore distorted data. Hard disk drives can pack more bits onto a platter if the bits don’t all have to work right. These markets (and probably certain others) have invested a lot of money in ECC research and development, and as a result ECC today is a very well-developed science.
Denali Software published a nice Continue reading “How 3D NAND Shrinks ECC Requirements”
Objective Analysis has just released a new report covering the nonvolatile dual inline memory module (NVDIMM) market in detail. This report, Profiting from the NVDIMM Market, explains the What, How, Why, & When of today’s and tomorrow’s NVDIMM products.
My readers know that I have been watching this market for some time, and that I am always perplexed as to whether to post about NVDIMMs in The Memory Guy or in The SSD Guy, since these products straddle the boundary between memory and storage. This time my solution is to publish posts in both!
The Objective Analysis NVDIMM market model reveals that the market for NVDIMMs is poised to grow at a 105% average annual rate to nearly 12 million units by 2021. This finding is based on a forecast methodology that has provided many of the most consistently-accurate forecasts in the semiconductor business. This forecast, and the report itself, were compiled through exhaustive research into the technology and the events leading up to its introduction, vendor and user interviews, and briefings from standards bodies.
This 80-page in-depth analysis examines all leading NVDIMM types and forecasts their unit and revenue shipments through 2021. Its 42 figures and 14 tables help Continue reading “New Report Details NVDIMM Market”
One of the most intriguing revelations during the Flash Memory Summit two weeks ago was Samsung’s new approach to stairstep etch in 3D NAND. This was one of numerous innovations the company’s EVP of Flash Products & Technologies, Kye Hyun (KH) Kyung, shared during Samsung’s Tuesday Morning keynote presentation.
The Memory Guy would point readers to the pdf of Samsung’s presentation on the Flash Memory Summit website, but it isn’t there, and it’s unlikely to ever be posted there. Samsung seems to have a policy that prohibits sharing such presentations.
Although I was unable to get a copy of the drawing that the keynoter used, I have tried to re-create it using, of all things, Excel! The result is the graphic for this blog post. The only thing I was unable to easily recreate was the different colors representing the layers of the 3D NAND. You’ll need to use your imagination and envision layers of two colors, with all the surfaces exposed on the top being the same color, but at different layers of a 64-layer structure.
Today’s common approach to 3D NAND’s stairstep is to etch a simple step pattern in one dimension, which I illustrated in an early 3D NAND blog post four years ago. This is a challenging Continue reading “How Samsung Will Improve 3D NAND Costs”
Yesterday’s news really underscored the race currently underway between 3D NAND makers to produce higher layer counts than one another.
Intel produced an announcement in which VP Rob Crooke bragged that: “Intel has delivered the world’s first commercially available 64-layer, TLC, 3D NAND solid state drive (SSD). While others have been talking about it, we have delivered.”
The announcement explained that the new Intel SSD 545s could be purchased at Newegg beginning that day.
The Memory Guy received Intel’s announcement at 10:02 AM Pacific Time. By 3:11 PM, five hours later, there was another announcement in my “In” box, this time from Western Digital (WDC).
WDC’s e-mail announced the development of the the SanDisk/Toshiba next-generation BiCS4 3D NAND technology, with 96 layers. The companies expect to begin to sample a 256Gb part to OEM customers in the second half of 2017 with production starting by the end of next year.
One has to wonder if WDC was Continue reading “3D NAND: “I Have More Layers than You Do!””
Most engineers never consider the weight of the firmware in their designs. You probably are saying to yourself: “Firmware doesn’t weigh anything!” In fact, you are wrong.
There is probably no application to which this is more important than the satellite industry. With payloads costing $20 – $40 per gram to launch into Earth orbit the weight of firmware becomes an enormously important part of the cost of putting a satellite into orbit.
Amplify this by the fact that a growing number of hardware-based functions are being replaced by their firmware equivalents, and by the fact that modularized firmware is being used to replace smaller hand-tuned subroutines with larger general-purpose routines, and you find that the number of ones and zeros in the average satellite is ballooning at a rate of more than ten times per year.
Is this bad? In this blog post The Memory Guy will put some numbers around the issue.
Firmware is stored as ones and zeros. In flash memory or DRAM these ones and zeros are stored either by adding Continue reading “Why Satellites Are Programmed Differently”
This week both the Toshiba-Western Digital team and Samsung disclosed details of their 64-layer 3D NAND designs at the IEEE’s International Solid-State Circuits Conference (ISSCC). The Memory Guy thought that it would be interesting to compare these two companies’ 64-layer chips against each other and against the one that Micron presented at last year’s ISSCC.
Allow me to point out that it’s no easy feat to get to 64 layers. Not only must the process build all 64 layers (or actually pairs of layers plus some additional ones for control) across the entire 300mm wafer with high uniformity and no defects, but then holes must be etched through varying materials from the top to the bottom with absolutely parallel sides at aspect ratios of about 60:1, that is, the hole is 60 times as deep as it is wide. After this the fab must deposit uniform layers of material onto the sides of these skinny holes without any variation in thickness.
None of these processes have ever been used to build any other semiconductor — it’s all brand new. This is what makes 3D NAND so challenging, and it’s why the technology is already 3 years behind its original schedule.
It’s not easy to tell from the conference papers whether or not Continue reading “64-Layer 3D NAND Chips Revealed at ISSCC”