The Memory Guy Blog - Jim Handy, Objective Analysis, on Semiconductor Memories

SLC to MLC to TLC to QLC to PLC: Diminishing Returns

From time to time The Memory Guy is asked to explain why the NAND flash business doesn’t immediately convert to the next larger number of bits per cell once it becomes available. Many people tend to think that a significant cost benefit will necessarily result from migrating to the next number of bits. It surprises these folks to find that the cost advantage of moving from TLC to QLC is only half as great as the benefit of moving from SLC to MLC.

There is a diminishing Continue reading “SLC to MLC to TLC to QLC to PLC: Diminishing Returns”

Symetrix: The Next Big Step for FeFETs

Ron Neale enjoyed an extensive e-mail correspondence with Professor Carlos Paz de Araujo of the University of Colorado in Colorado Springs, and founder of Symetrix, about Symetrix’ new approach to ferroelectric memory technology. In this post Ron provides an overview of that conversation that provides significant insight into why FRAMs hit their limit at 180nm, and why they suddenly have opportunities at the most advanced process lithographies.

Ferroelectric memory was one of the earliest and first of the non-volatile (NV) emerging memory technologies to make significant Continue reading “Symetrix: The Next Big Step for FeFETs”

White Paper: The Future of Low-Latency Memory

Tom Coughlin and I have just published a new white paper that is now available on the Objective Analysis website. It examines the way that processors communicate with DRAM, and how problems that stem from loading get in the way of increasing speed.

We compare DDR against HBM (High Bandwidth Memory) and a newer Continue reading “White Paper: The Future of Low-Latency Memory”

Putting the Brakes on Added Memory Layers

For some time two sides of the computing community have been at odds. One side aims to add layers to the memory/storage hierarchy while other side is trying to halt this growth.

This has been embodied by recent attempts to stop using objective nomenclature for cache layers (L1, L2, L3) and moving to more subjective names that aim to limit any attempt to add another new layer.

This is a matter close to my heart, since Continue reading “Putting the Brakes on Added Memory Layers”

Micron Bows Out of 3D XPoint Business

In an investor conference call today Micron Technology announced that it would discontinue further development of the 3D XPoint memory that the company had developed in partnership with Intel, phasing out production and selling off the Lehi, Utah fab (pictured) that makes 3D XPoint.

Micron said that it has determined that the market for the product is too small to Continue reading “Micron Bows Out of 3D XPoint Business”

ZnTe Selectors to Solve NVM Fabrication Problems

Contributor Ron Neale joins us again to review a recently-published article in the journal Nature Scientific Reports. While the main focus of the paper is on using a nitrogen environment to generate stable memory selectors from ZnTe, it also provides some new inputs through which he finds further support of his theories of Forming and device behavior.

A recently-published Nature Scientific Reports article by a research team from Hanyang and Kunsan Universities in The Republic of Korea focuses on Continue reading “ZnTe Selectors to Solve NVM Fabrication Problems”

Microchip’s Answer to Emerging Memories

Microchip Technology is now shipping a memory chip that has been designed to provide the most popular features of emerging memory chips without using any non-standard semiconductor technologies. It’s as fast as an SRAM with the nonvolatility of an EEPROM.

Readers may recall that Tom Coughlin and I recently updated Continue reading “Microchip’s Answer to Emerging Memories”

Why 3D NAND is Stuck at 40nm

I recently was asked how much 3D NAND pitches had shrunk since the technology’s 2013 introduction. Samsung made a big to-do about using 40nm back in 2015, but the company and its competitors don’t seem to have given an update since then. Shouldn’t it have gone to smaller processes like 35nm, 25nm, 20nm, etc.?

The Memory Guy’s reply was that it’s nearly impossible Continue reading “Why 3D NAND is Stuck at 40nm”

The Invention of Charge Trap Memory – John Szedon

A significant transition has occurred over the past few years that many people don’t know about: Flash memory has moved almost wholesale from the floating gate bit cells, the process that they had always used before, to charge trap bit cells.

Until 2002 all flash used a floating gate. That year partners AMD & Fujitsu, who later merged Continue reading “The Invention of Charge Trap Memory – John Szedon”

SK hynix Acquires Intel’s NAND Business

SK hynix and Intel today announced that SK hynix will acquire Intel’s NAND flash business for $9 billion. SK hynix gets Intel’s business, its manufacturing plant with two fabs in Dalian, China, and all of Intel’s designs and intellectual property. The Memory Guy thinks this is a pretty good deal all around.

Intel doesn’t do well in Continue reading “SK hynix Acquires Intel’s NAND Business”