It’s pretty easy to go from talking about the earliest 24-layer 3D NAND to talking about the next-generation 32-layer 3D NAND, and then to progress through 48, 64, and more layers, but the amazing scale of a 96-layer part doesn’t really sink in when you just talk about numbers.
That’s why The Memory Guy was so charmed when Western Digital Corp. (WDC) invited me in for a briefing that gave me a more solid idea of how significant of a number 96 really is. The company brought along a plastic model that replicated the structure of its 96-layer BiCS NAND chip using clear plastic which was dramatically lighted from the inside.
WDC’s model was constructed using standard plastic sheeting, probably 1/8″ thick (~3mm), one sheet to represent the conductive polysilicon and one to represent the insulating silicon dioxide for each layer. Naturally, there are more than 96 layers in 96-layer NAND since there are source select transistors at the bottom and drain select transistors at the top. This adds a little bit to the layer count.
Another layer in the middle of Continue reading “96-Layer NAND in Perspective: WDC Video”
One of the most intriguing revelations during the Flash Memory Summit two weeks ago was Samsung’s new approach to stairstep etch in 3D NAND. This was one of numerous innovations the company’s EVP of Flash Products & Technologies, Kye Hyun (KH) Kyung, shared during Samsung’s Tuesday Morning keynote presentation.
The Memory Guy would point readers to the pdf of Samsung’s presentation on the Flash Memory Summit website, but it isn’t there, and it’s unlikely to ever be posted there. Samsung seems to have a policy that prohibits sharing such presentations.
Although I was unable to get a copy of the drawing that the keynoter used, I have tried to re-create it using, of all things, Excel! The result is the graphic for this blog post. The only thing I was unable to easily recreate was the different colors representing the layers of the 3D NAND. You’ll need to use your imagination and envision layers of two colors, with all the surfaces exposed on the top being the same color, but at different layers of a 64-layer structure.
Today’s common approach to 3D NAND’s stairstep is to etch a simple step pattern in one dimension, which I illustrated in an early 3D NAND blog post four years ago. This is a challenging Continue reading “How Samsung Will Improve 3D NAND Costs”
Yesterday’s news really underscored the race currently underway between 3D NAND makers to produce higher layer counts than one another.
Intel produced an announcement in which VP Rob Crooke bragged that: “Intel has delivered the world’s first commercially available 64-layer, TLC, 3D NAND solid state drive (SSD). While others have been talking about it, we have delivered.”
The announcement explained that the new Intel SSD 545s could be purchased at Newegg beginning that day.
The Memory Guy received Intel’s announcement at 10:02 AM Pacific Time. By 3:11 PM, five hours later, there was another announcement in my “In” box, this time from Western Digital (WDC).
WDC’s e-mail announced the development of the the SanDisk/Toshiba next-generation BiCS4 3D NAND technology, with 96 layers. The companies expect to begin to sample a 256Gb part to OEM customers in the second half of 2017 with production starting by the end of next year.
One has to wonder if WDC was Continue reading “3D NAND: “I Have More Layers than You Do!””