Tag: Cross-point

Crossbar or Crosspoint?

Computing Crossbar SwitchThe Memory Guy has recently run across a point of confusion between two very similar terms: Crossbar and Crosspoint.

A crosspoint memory is a memory where a bit cell resides at every intersection of a wordline and a bitline.  It’s the smallest way you can make a memory cell.  Think of the wordlines and bitlines as the wires in a window screen.  If there’s a bit everywhere they cross, then it’s a crosspoint memory.

In most cases a crossbar is a communication path in a computing system.  (Of course, there are exceptions, the main one being a company, Crossbar Inc., that is developing a crosspoint memory technology!) A crossbar communication path is topographically similar to a crosspoint, but its function is to connect a number of memory arrays to a number of processors.  Visualize a vertical column of memory arrays named A, B, C… and a horizontal row of processors named 1, 2, 3… as is illustrated in this post’s graphic.  The crossbar can connect Processor 1 to Memory A, or to any other memory that is not already connected to another processor.  These connections are represented by the circles in the diagram.  You can see that this is an efficient way to allow processors to share a memory space to achieve very high speed inter-processor communications.

Crossbars are quite likely to Continue reading “Crossbar or Crosspoint?”

Micron/Intel 3D XPoint Raises More Questions than Answers

Micron-Intel 3D XPoint Memory InternalsMicron and Intel hosted an event in San Francisco Tuesday, July 28, to introduce a new memory technology that they have named “3D XPoint”.  This technology was explained to be “up to 1,000 times faster, with 1,000 times the endurance of NAND flash” while being significantly cheaper than DRAM.

Some technical details:

  • 3D XPoint is a “Fundamentally Different Technology” than current memory types.  It’s an ReRAM that uses material property changes for bit storage where both DRAM and NAND use charge to store a bit
  • The chip currently stores 128Gb in two stacked planes of 64Gb each, storing a single bit per cell
    • Today’s densest production NAND flash chips store 128GB by using MLC, so this chip actually has twice as many bit cells as any production NAND flash
    • The companies do not see a clear limit to the number of planes they can stack, but are optimistic about this
  • The bulk mechanism can be used to store multiple bits on a single cell (MLC)
  • Today’s chip is made using a 20nm process, but can scale well past that
    • There is no clear limit of how far the technology can be scaled
  • It’s 1,000 times faster than NAND flash and offers 1,000 times NAND’s endurance
  • It’s 10 times as dense as today’s “Conventional Memory” (which I suppose to be DRAM)
  • This is not intended to replace either NAND or DRAM, but to coexist as a new memory layer between NAND and DRAM

The companies claim that other Continue reading “Micron/Intel 3D XPoint Raises More Questions than Answers”