With the release of its Cascade Lake family of processors today (formally called the “2nd Generation Intel Xeon Scalable processor”) Intel disclosed more details about its Optane DIMM, which has been officially named the “Intel Optane DC Persistent Memory.” This DIMM’s architecture is surprisingly similar to an SSD, even to the point of its having error correction and encryption!
The Memory Guy doesn’t generally cover SSDs, but I do cover DIMMs, so this is one of those posts that I could have put into either of my blogs: The Memory Guy or The SSD Guy. I have decided to put it here with the hopes that it will be easier for members of the memory community to find.
The internal error correction, the encryption, and the fact that 3D XPoint Memory wears out and must use wear leveling, all cause the Optane DIMM’s critical timing path to be slower than the critical path in a DRAM DIMM, rendering the Optane DIMM unsuitable for code execution. This, and the fact that XPoint writes are slower than its reads, all help to explain why an Optane DIMM is never used as the only memory in a system: there is always a DRAM alongside the Optane DIMM to provide faster Continue reading “What’s Inside an Optane DIMM?”
Ever since moving to Silicon Valley some time ago The Memory Guy has worked with a number of impressively-talented engineers from India. Some are educated in the US, while others are educated in India. One university that produces excellent engineers is the Indian Institute of Technology, or IIT.
It comes as no surprise, then, to find a valuable resource produced by an IIT faculty member. Dr. Sparsh Mittal, an assistant professor at IIT Hyderabad, reached out to me to share some papers that he thought might be of interest to Memory Guy readers. They were a few of roughly 40 papers that he has posted on his publications page. He explained that he previously worked at Oak Ridge National Lab, in the US.
Dr. Sparsh has published several very comprehensive surveys on memory systems, both conventional and emerging, covering topics like DRAM reliability, NVM/Flash, ReRAM-based processing-in-memory, and the architecture of neural networks. The web page lists 34 surveys, eight of them Continue reading “Valuable Memory Technical Resources”
Error Correction Codes, ECC, are not only important to today’s NAND flash market, but they have been a cause of concern to NAND users for a number of years. The Memory Guy has been intending for some time to write a low-level primer on ECC, and I am finally getting it done!
Why is ECC necessary on NAND flash, yet it’s not used for other memory technologies? The simple answer is that NAND’s purpose is to be the absolute cheapest memory on the market, and one way to achieve the lowest-possible cost is to relax the standards for data integrity — to allow bit errors every so often. This technique has been used for a long time in both communications channels and in hard disk drives. Data communication systems can transfer more data using less bandwidth and a weaker signal over longer distances if they use error correction to restore distorted data. Hard disk drives can pack more bits onto a platter if the bits don’t all have to work right. These markets (and probably certain others) have invested a lot of money in ECC research and development, and as a result ECC today is a very well-developed science.
Denali Software published a nice Continue reading “How 3D NAND Shrinks ECC Requirements”