(Excerpted from an Objective Analysis Alert issued 1 December 2014.)
In a move touted as a merger of equals, Cypress will acquire Spansion in an all-stock transaction slated to close in the second quarter of 2015. The purchase price is estimated at $1.6 billion.
Cypress points out that it is the leading producer of SRAMs, and that Spansion is the leading NOR flash provider.
One striking feature of this transaction is the Continue reading “Cypress to Merge with Spansion”
The Memory Guy was recently asked about using memories in a satellite. What would be a good technology to use in a space application?
The problem with space is that there is a lot of radiation. Radiation on the earth’s surface is lower because it is stopped by the atmosphere, but in space there is an abundance of radiation that interferes with most semiconductors. Radiation is also a concern in certain medical applications where a memory must maintain its contents while undergoing sterilization through irradiation. Experiments on conventional flash memories have shown data loss at only 2% of the Continue reading “Memory Issues in Space & Medical Applications”
Intel and Micron today announced that the new version of Intel’s Xeon Phi, a highly parallel coprocessor for research applications, will be built using a custom version of Micron’s Hybrid Memory Cube, or HMC.
This is only the second announced application for this new memory product – the first was a Fujitsu supercomputer back in November.
For those who, like me, were unfamiliar with the Xeon Phi, it’s a module that uses high core-count processors for problems that can be solved with high degrees of parallelism. My friend and processor guru Nathan Brookwood tells me Continue reading “Intel to Use Micron Hybrid Memory Cube”
At the Flash Memory Summit yesterday ES Jung, PhD, EVP & GM for the Samsung R&D Center, explained the inner workings of Samsung’s new V-NAND vertical NAND flash technology. I will shortly be writing a series to explain what a 3D NAND is since there is little on the web that gives clear details about the technology.
One key attribute of most 3D NAND approaches is the use of a charge trapping layer. This has to do with the difficulty of manufacturing sideways floating gates.
Dr Jung delighted the show’s audience by explaining that a standard floating gate is like Continue reading “Samsung’s View on Charge Trap Flash”