With Intel’s Cascade Lake rollout last month came with a co-introduction of 3D XPoint Memory in a DIMM form factor, the Optane DIMM that had been promised since the first introduction of 3D XPoint Memory in mid-2015. A lot of benchmarks were provided to make the case for using Optane DIMMs (formally known as the Intel Optane DC Persistent Memory), but not much was said about the pricing, except for assertions that significant savings were possible when Optane was used to replace some of the DRAM in a large computing system.
So… How much does it cost? Well certain technical reports in resources like Anandtech probed sales channels to see what they could find, but The Memory Guy learned that the presentations Intel made to the press in advance of the Cascade Lake rollout contained not only prices for the three Optane DIMM densities (128, 256, & 512GB), but also provided the prices of the DRAM DIMMs that they were being compared against. I’ll get to that in a moment, but first let’s wade through the fundamentals of Intel’s Optane pricing strategy to understand why Intel has needs to price it the way that it has.
In Objective Analysis’ report on 3D XPoint Memory, and in several presentations I have Continue reading “Intel’s Optane DIMM Price Model”
For more than a year The Memory Guy has been fielding questions about Micron’s QuantX products.
First announced at the 2016 Flash Memory Summit, this brand name has been assigned to Micron SSDs and DIMMs that use the Intel/Micron 3D XPoint Memory. Originally QuantX products were scheduled to ship in 2017, but Micron is currently projecting availability in 2019. My clients wonder why there have been these delays, and why Micron is not more actively marketing this product.
The simple answer is that it doesn’t make financial sense for Micron to ship these products at this time.
Within two weeks of the first announcement of 3D XPoint Memory, at the 2015 Flash Memory Summit, I knew and explained that the technology would take two years or more to reach manufacturing cost parity with DRAM, even though Intel and Micron loudly proclaimed that it was ten times denser than DRAM. This density advantage should eventually allow XPoint manufacturing costs to drop below DRAM costs, but any new technology, and even old technologies that are in low-volume production, suffer a decided scale disadvantage against DRAM, which sells close Continue reading “Where is Micron’s QuantX?”
At the International Solid State Circuits Conference (ISSCC) last week a new “Last Level Cache” was introduced by a DRAM company called “Piecemakers Technology,” along with Taiwan’s ITRI, and Intel.
The chip was designed with a focus on latency, rather than bandwidth. This is unusual for a DRAM.
Presenter Tah-Kang Joseph Ting explained that, although successive generations of DDR interfaces has increased DRAM sequential bandwidth by a couple of orders of magnitude, latency has been stuck at 30ns, and it hasn’t improved with the WideIO interface or the new TSV-based High Bandwidth Memory (HBM) or the Hybrid Memory Cube (HMC). Furthermore, there’s a much larger latency gap between the processor’s internal Level 3 cache and the system DRAM than there is between any adjacent cache levels. The researchers decided to design a product to fill this gap.
Many readers may be familiar with my bandwidth vs. cost chart that the Memory Guy has used to introduce SSDs and 3D XPoint memory. The gap that needs filling is Continue reading “Is Intel Adding Yet Another Memory Layer?”