It’s earnings call season, and we have heard of a slowing DRAM market and NAND flash price declines from Micron, SK hynix, Intel, and now Samsung. DRAM prices have stopped increasing, and that can be viewed as a precursor to a price decline.
Samsung’s 31 October, 2018 3Q18 earnings call vindicated Objective Analysis‘ forecast for a 2H18 downturn in memories that will take the rest of the semiconductor market with it.
Those familiar with our forecast know that for a few years we have been predicting a downturn in the second half of this year as NAND flash prices fall, followed by a DRAM price collapse. After the DRAM collapse the rest of the semiconductor market will undergo a downturn.
We’ve been calling for this downturn for some time. Dan Hutcheson at VLSI Research has been videotaping our forecast every December for the past Continue reading “Memory Market Falling, as Predicted”
On Saturday, June 18, Samsung’s Xian fab, the only facility in the world currently producing 3D NAND flash, suffered a power failure. How much of a problem is this?
The answer really depends upon who you ask. An article in the Financial Express quoted Samsung as saying that it would have a minimal impact, and that full-scale operations should resume in a few days. The article also said that Samsung estimated that the wafer loss would be below 10,000 wafers.
Assuming that the entire loss consisted of Samsung’s most advanced 48-layer 256Gb 3D NAND a 10,000-wafer loss would be less than 1% of total industry gigabyte shipments.
Korea Times quoted an anonymous fund manager who said: “The one-time incident will cost Samsung up to 20 billion won, which is very minimal. It won’t make heavy impact on Samsung’s chip business and the entire industry.”
According to Korean news source Chosenilbo the outage was caused by Continue reading “Samsung Power Glitch – Is It Important?”
Let’s look at how one form of 3D NAND is manufactured. For this post we will explore the original design suggested by Toshiba at the IEEE’s International Electron Device Meeting (IEDM) in 2007. It’s shown in the first graphic of this post. (Click on any of the graphics for a better view.)
Toshiba calls this technology “BiCS” for “Bit Cost Scaling.” The technique doesn’t scale the process the way the world of semiconductors has always done to date – it scales the cost without shrinking the length and width of the memory cell. It accomplishes this by going vertically, as is shown in this post’s first graphic.
This takes a special effort. This is where the real Continue reading “3D NAND: Making a Vertical String”
The December issue of the IEEE Spectrum includes a fascinating article about a 100 million cycle flash memory developed by Macronix. The company will present this design at at IEDM this month.
In brief: Macronix’ researchers buried a heater in the array to heat the tunnel dielectric, annealing out the disruptions & traps that might cause a bit to fail.
A prototype has so far been tested more than 100 million cycles and it shows no sign of impending failure. Researchers believe that it is likely to reach one billion or more cycles, but such testing will take several months. This just may be able to Continue reading “Macronix Solves Flash Wear Problem”
Macronix, a company known for its leadership in mask ROMs and low-density NOR flash has just entered the NAND flash market. This adds a new player to a very small pool of competitors: Samsung, Toshiba, SanDisk, Hynix, Intel, and Micron.
The company’s first NAND products are SLC chips of two densities: 512Mb and 1Gb. Compare this to the offerings of the market’s other participants which range up to 256Gb. Spot price tracker InSpectrum doesn’t even track pricing of densities below 4Gb!
There still seems to be a good market for these low-density parts: According to WSTS Continue reading “New NAND Player: Macronix”