3D NAND: Who Will Make It and When?

SK hynix 3D NAND Cross SectionThis series has looked at 3D NAND technology in a good deal of technical depth.  The last question to be answered centers around the players and the timing of the technology.  A lot has been said about the technology and its necessity.  Will everyone be making 3D NAND?  When will this big transition occur?

This post will provide an update as of its publication (13 December 2013) to show each company’s current status, to the best of The Memory Guy’s understanding.  Readers may want to refer back to the earlier posts in this series, as well as to a June 2013 Nikkei TechON article that gives a good review of the 3D NAND alternatives that have been presented at various technical conferences.

Let’s start with Samsung, the largest producer of NAND flash today.  Just prior to Memcon 2013 last Continue reading “3D NAND: Who Will Make It and When?”

Rambus and Micron Sign License Agreement

The following is excerpted from an Objective Analysis Alert that can be downloaded from the company’s website.

Micron Licenses Rambus IPRambus and Micron announced on Tuesday that they have signed a patent cross license agreement.  Micron receives rights to Rambus IC patents, including memories.  Both Micron and Elpida products will be covered.  The companies have thus settled all outstanding patent and antitrust claims in their 13-year court battle.

Micron will make royalty payments to Rambus of up to $10 million per quarter over the next seven years, totaling $280 million, after which Micron will receive a perpetual, paid-up license.

Rambus and Micron both have Continue reading “Rambus and Micron Sign License Agreement”

How Do You Erase and Program 3D NAND?

How FN Tunneling WorksSome of my readers have asked: “How is 3D NAND programmed and erased?  Is it any different from planar NAND?”

In a word: No.

(Before I get too far into this allow me to admit that The Memory Guy doesn’t understand quantum physics, so I will be presenting this only to the depth that I understand it.  There will be no band-gap diagrams or equations to wrestle with.)

Both 3D NAND and planar NAND use Fowler Nordheim Tunneling (FN) to both program and erase.  This differs from NOR flash which programs bits using Continue reading “How Do You Erase and Program 3D NAND?”

3D NAND: How do You Access the Control Gates?

Samsung's TCAT NAND Flash Wordline COnnectionsOne of the thornier problems in making 3D NAND is the job of connecting the peripheral logic (the row decoders) to all of those control gates that are on layers buried somewhere within the bit array.  Remember that the control gates are the conductive sheets of polysilicon or tantalum nitride at various depths in the chip.

The problem boils down to this: You can’t run connections from each layer up or down the side of the chip to get to the CMOS circuits below.  Instead you have to create a terrace structure to expose and connect to each layer.

These connections are made by etching a stair-step pattern into the layers and sinking Continue reading “3D NAND: How do You Access the Control Gates?”

An Alternative Kind of Vertical 3D NAND String

Samsung's TCAT 3D NAND flashMy prior 3D NAND post explained how Toshiba’s BiCS cell works, using a silicon nitride charge trap to substitute for a floating gate.  This post will look at an alternative technology used by Samsung and Hynix which is illustrated in the first graphic, a diagram Samsung presented at a technical conference. This cell also uses a charge trap.

Let The Memory Guy warn you, if the process in my prior post seemed tricky, this one promises to put that one to shame!

Part of this stems from the use of a different kind of NAND bit cell.  You can shrink flash cells smaller if you use a high-k gate dielectric (one with a high dielectric constant “k”) since it Continue reading “An Alternative Kind of Vertical 3D NAND String”

3D NAND: Making a Vertical String

Toshiba's Original BiCS Diagram - IEDM 2007Let’s look at how one form of 3D NAND is manufactured.  For this post we will explore the original design suggested by Toshiba at the IEEE’s International Electron Device Meeting (IEDM) in 2007.  It’s shown in the first graphic of this post.  (Click on any of the graphics for a better view.)

Toshiba calls this technology “BiCS” for “Bit Cost Scaling.”  The technique doesn’t scale the process the way the world of semiconductors has always done to date – it scales the cost without shrinking the length and width of the memory cell.  It accomplishes this by going vertically, as is shown in this post’s first graphic.

This takes a special effort. This is where the real Continue reading “3D NAND: Making a Vertical String”

What is 3D NAND? Why do we need it? How do they make it?

3D NANDIn August 2013 Samsung announced its V-NAND, the first production 3D NAND, kicking off a big change in the way that NAND flash will be manufactured.  This new technology raises a number of important questions:

  • What exactly is a 3D NAND?
  • Why does the industry need to go to a 3D topology?
  • How the heck do they make such a product?

To answer these questions I assembled a series of articles posted as weekly segments on The Memory Guy blog during the fourth quarter of 2013.  The different sections are listed below, with hot links to each section.

Each of these is a topic that is complex enough to warrant its own post, so for the nine Fridays I published a post to explain each one in depth.  I hope you find it engaging and informative.

Micron Samples Hybrid Memory Cube

Close-Up of Micron's Hybrid Memory CubeToday Micron Technology announced that it is sampling the Hybrid Memory Cube (HMC) a DRAM packaging technology that it has been working on with the HMC Consortium.

Micron has been pushing to rapidly advance the HMC’s development and seems to have reached this point in an impressively brief time, given the complexity of the technology.  It has only been two years since the first public appearance of the HMC at the 2011 Intel Developer Forum.

Some pretty advanced technology was used to make this product.  DRAM processes are not very good at Continue reading “Micron Samples Hybrid Memory Cube”

Micron NAND Reaches 16nm

Die Photo of Micron 16nm 128Gb NAND chipMicron has announced that it is sampling a new 128Gb NAND flash chip based upon a 16nm process, with production slated for the fourth quarter.  To The Memory Guy’s knowledge this is the tightest process available.

The company, with its partner Intel, gained a lead with its 20nm process generation through its use of a Hi-k tunnel dielectric, a new material that replaces more conventional silicon dioxide layer with a new material (Micron won’t say what) that yields the same capacitance with a thinner layer.  This has become very important with today’s tight processes because of issues of inter-cell interference.

Other NAND makers are migrating to Continue reading “Micron NAND Reaches 16nm”

SanDisk & Toshiba Move to Next Process Node

SanDisk's explanation of old vs new 19nm processesSanDisk and Toshiba, in separate announcements, both today disclosed their next-generation process technology.

The companies introduced their new “1y” processing node that, according to SanDisk, produces 19nm x 19.5nm cell, versus the earlier “19nm” process (or “1x”) that used a 19nm x 26nm cell.

The graphic for this post (click to enlarge) was presented during SanDisk’s May 5th Analyst Day and compares the 24nm process to the 19 x 26nm process, moving to the 19 x 19nm process, and eventually to “1z” which neither company is yet revealing.  After the 1z process SanDisk believes Continue reading “SanDisk & Toshiba Move to Next Process Node”