In this first post of a five-part series contributor Ron Neale analyzes selector technologies presented by CEA Leti at the 2018 IEDM conference last December.
At the close of last year the IEDM maintained its long-standing reputation for offering across-the-board the right focus at the right time on important and key parts of the electronic device discipline. For those with an interest in the future of stacked or 3D NV-memory arrays there were a number of important papers and presentations on a variety of thin film memory selectors or matrix isolation devices (MIDs).
Important, because as the move towards stacked memory arrays for storage class memory (SCM) and persistent memory (PM) applications gains momentum, the thin film selector may be the device which is key in determining the performance and reliability for a number of different types of NV memory arrays or even the very existence of that type of memory array. One of the important and poorly understood variables in the mix is the selector forming voltage and the structural changes which lead from it to the operating device threshold voltage which, in my view needs a lot more by way of detailed understanding.
As the memory array moves into Continue reading “NV Stacked Memory: Selectors and Forming (Part 1)”
This is Part 4 of a series contributed by Ron Neale to the Memory Guy blog, in which Ron looks into some important detailed analytical work by a joint team at IBM and Yale University which might point to the way of achieving improved PCM endurance.
I want, in this final part, to focus on its possible implications for commercial PCM products.
When Intel and Micron first introduced 3D XPoint Memory the companies claimed that it would be 1,000 times as fast as flash memory with 1,000 times the endurance at ten times the density of standard memory (meaning DRAM). Now that Intel’s XPoint-based Optane SSDs have been released and their specifications are public we can estimate what the technology’s endurance might be.
The table below, explained in another Memory Guy blog post, gives estimates of best-case endurance for the cells in the XPoint memory in Optane SSDs. In other words, with a sophisticated enough controller, good DRAM buffering, and overprovisioning, all of which are techniques commonly used to extend the life of the media in a NAND flash SSD, the cell lifetime could be significantly lower than that shown in the last column of the table and the SSD would still provide the specified endurance. (These techniques are explained in detail in an SSD Guy blog post series for anyone who is interested in understanding them.)
As the calculated Continue reading “Extending the Write/Erase Lifetime of Phase Change Memory: Part 4 – The Possible Implications for 3D XPoint and Optane”
For a number of years The Memory Guy has wanted to find a copy of the 1970 article, published in Electronics magazine, in which Intel’s Gordon Moore and two authors from Energy Conversion Devices, Ron Neale and D.L. Nelson, showed that PCM could be used as a memory device. After all, this is the technology behind Micron & Intel’s 3D XPoint Memory.
The cover of the magazine (this post’s graphic) has been used by Intel to promote its PCM or PRAM chips before those were spun off to Numonyx (now a part of Micron). Intel, though, didn’t appear to have anything to share but the cover photo.
Electronics magazine went out of business in 1995, and that makes the task of finding archive copies more challenging.
It recently occurred to me that the best person to ask might be the article’s lead author, Ron Neale, who has been a regular contributor to EE Times and who now also contributes blog posts to The Memory Guy.
I was astounded to discover that Continue reading “Original PCM Article from 1970”