Optane

Emerging Memories Today: Process Equipment Requirements

Emerging Memory ParadeSomething that distinguishes the Emerging Memory report that Tom Coughlin and I recently published is the depth in which we cover in the field.  This is not measured in pages, but in the topics that we cover.  For example, this blog post, excerpted from the report, covers the changes in tooling that will be necessary to allow a standard CMOS wafer fabrication plant (a “fab”) to produce an emerging memory technology, and the impact that this is likely to have on the market for semiconductor tools.

All of the emerging memory technologies covered in the Memory Guy’s previous post share certain things in common.  One of them is that they are built between metal layers, rather than in the silicon CMOS substrate itself (with the possible exception of the hafnium oxide FRAM.)

This means that the tooling required for any of these technologies will bear a strong resemblance to that used by any of the others.  For the most part these tools will be used for deposition and etch.  The lithography requirements will be satisfied by the tools used to pattern the metal layers.

The process flow in this figure sheds some light on the steps that Continue reading

Emerging Memories Today: The Technologies: MRAM, ReRAM, PCM/XPoint, FRAM, etc.

Emerging Memory ParadeHere in the US we use an extremely odd expression.  If there are multiple varieties of an item we commonly say: “There are more of them than you can shake a stick at!”  This is a very lengthy way to say: “numerous.”  (I don’t believe that ANYONE understands how that expression became a part of our vernacular!)  Although The Memory Guy isn’t normally seen shaking a stick, I find it an apt way to describe the numerous new memory technologies that are being pioneered today.  There are certainly lots of them!

This post is intended to be very high-level technical description of today’s leading emerging memory technologies.  These are excerpts of the in-depth descriptions that can be found in our recently-released report: Emerging Memories Poised to Explode.

PCM: Also known as PRAM, Phase-Change Memory technology is based upon a material that can be either amorphous or crystalline at normal ambient temperatures.  The crystalline state has a low resistance and the amorphous state has a high resistance.  This is controlled by melting the bit cell by passing a current though it and then allowing it to cool at different rates.

In chemistry and physics, anything with a Continue reading

Emerging Memories Today: Understanding Bit Selectors

Emerging Memory ParadeThe previous post in this series (excerpted from the Objective Analysis and Coughlin Associates Emerging Memory report) explained why emerging memories are necessary.  Oddly enough, this series will explain bit selectors before defining all of the emerging memory technologies themselves.  The reason why is that the bit selector determines how small a bit cell can get, and that is a very significant component of the overall cost of the technology.  Cost, of course, is extraordinarily important because no system designer would use a component that would make a system more expensive than it absolutely needs to be!

A number of the Memory Guy’s readers may never have heard of a selector. I’ll explain it here.  It’s not complicated.

Every bit cell in a memory chip requires a selector.  This device routes the bit cell’s contents onto a bus that eventually makes its way to the chip’s pins, allowing it to be read or written.  The bit cell’s technology determines the type of selector that is appropriate: SRAMs use two transistors, DRAMs use one transistor, and flash memories combine a transistor with the Continue reading

Emerging Memories Today: Why Emerging Memories are Necessary

Emerging Memory ParadeNon-silicon memory technologies have been studied for about as long as have silicon-based technologies, but the silicon technologies have always been preferred.  Why is that, and why should anything change?

This is a question that The Memory Guy is often asked.  The answer is relatively simple.

Silicon memory technologies benefit from the fact that they have always been manufactured on process technologies that are nearly identical to those used to produce CMOS logic, and can therefore take advantage of the advancements that are jointly developed for both memory and logic processes.  In fact, before the middle 1980s, logic and memory processes were identical.  It wasn’t until then that the memory market grew large enough (over $5 billion/year) that it could support any additional process development on its own.

Even so, memory processes and logic processes are more similar than different.  This synergy between memory and logic continues to reduce the process development cost for both memories and logic.

Emerging memories depart from Continue reading

Emerging Memories Today: New Blog Series

Emerging Memory ParadeThere’s never been a more exciting time for emerging memory technologies. New memory types like PCM, MRAM, ReRAM, FRAM, and others have been waiting patiently, sometimes for decades, for an opportunity to make a sizeable markets of their own.  Today it appears that their opportunity is very near.

Some of these memory types are already being manufactured in volume, and the established niches that these chips sell into can provide good revenue.  But the market is poised to experience a very dramatic upturn as advanced logic processing nodes drive sophisticated processors and ASICs to adopt emerging persistent memory technologies.  Meanwhile Intel has started to aggressively promote its new 3D XPoint memory for use as a persistent (nonvolatile) memory layer for advanced computing.  It’s no wonder that SNIA, JEDEC, and other standards bodies, along with the Linux community and major software firms are working hard to implement the necessary standards and ecosystems to support widespread adoption of the persistent nature of these new technologies.

This post introduces a Continue reading

Extending the Write/Erase Lifetime of Phase Change Memory: Part 4 – The Possible Implications for 3D XPoint and Optane

Ron NealeThis is Part 4 of a series contributed by Ron Neale to the Memory Guy blog, in which Ron looks into some important detailed analytical work by a joint team at IBM and Yale University which might point to the way of achieving improved PCM endurance.


I want, in this final part, to focus on its possible implications for commercial PCM products.

When Intel and Micron first introduced 3D XPoint Memory the companies claimed that it would be 1,000 times as fast as flash memory with 1,000 times the endurance at ten times the density of standard memory (meaning DRAM).  Now that Intel’s XPoint-based Optane SSDs have been released and their specifications are public we can estimate what the technology’s endurance might be.

The table below, explained in another Memory Guy blog post, gives estimates of best-case endurance for the cells in the XPoint memory in Optane SSDs.  In other words, with a sophisticated enough controller, good DRAM buffering, and overprovisioning, all of which are techniques commonly used to extend the life of the media in a NAND flash SSD, the cell lifetime could be significantly lower than that shown in the last column of the table and the SSD would still provide the specified endurance.  (These techniques are explained in detail in an SSD Guy blog post series for anyone who is interested in understanding them.)

As the calculated Continue reading

Extending the Write/Erase Lifetime of Phase Change Memory: Part 2 – A More Complete View of Element Separation

Ron NealeThis is Part 2 of a short Memory Guy series in which contributor Ron Neale continues to explore the possible future impact on PCM memory performance, especially write/erase endurance, building on the results of the IBM/Yale University analysis outlined in Part 1.


After, in Part 1, summarizing the methodology my next step was to try to bring together in another simple diagram all the detail of the complexity of  the movement of the different elements of the phase change memory material at different locations within the memory cell which the IBM/Yale work has disclosed. Movement which leads to the conclusion that bi-polar operation would be means of extending PCM endurance.

In this post’s first diagram (below) the central region provides illustration of the paper’s unique PCM device structure: A high aspect ratio tapered cell lined with a metal conductor. With the two-state memory switching region located (red coloured) roughly at the centre of the taper.  This means that, Continue reading

Extending the Write/Erase Lifetime of Phase Change Memory: Part 1- PCM Element Separation and Endurance

Ron NealeThis is the first of a new line-up of Memory Guy posts by Ron Neale.   In this 4-part series Ron takes a look at the recently-published analysis by a team from IBM and Yale University (Wiley: Communications of Advanced Materials, Volume 30, Issue 9, March 1, 2018 “Self-Healing of a Confined Phase Change Memory Device with a Metallic Surfactant Layer,” Xie et al) which has cast some new light on the complexity of the movement and element separation in phase change memory (PCM) device structures.


In this series of articles I will briefly review what I think is an important piece of work and its implications for the future of  PCM write/erase (w/e) endurance in commercial PCM memory arrays. Today’s production Phase-Change Memory, the basis of the Intel/Micron 3D XPoint Memory, wears out faster than expected.  This series will investigate some of the potential reasons for this discrepancy.

Back in 2016 a research team led by IBM claimed the world record for PCM w/e endurance of  greater than 2 x 10E12 cycles (ALD-based Confined PCM with a Metallic Liner Toward Unlimited Endurance, Proc IEDM 2016 ). As of today commercially available PCM memory arrays offer w/e endurance of some six orders of magnitude less.  The table below Continue reading

Latest White Paper: New Memories for Efficient Computing

A Potpourri of Emerging MemoriesThere has been a lot of discussion in the trade press lately about new memory technologies.  This is with good reason: Existing memory technologies are approaching a limit after which bits can’t be shrunk any smaller, and that limit would put an end to Moore’s Law.

But there are even more compelling reasons for certain applications to convert from today’s leading technologies (like NAND flash, DRAM, NOR flash, SRAM, and EEPROM) to one of these new technologies, and that is the fact that the newer technologies all provide considerable energy savings in computing environments.

Objective Analysis has just published a white paper that can be downloaded for free which addresses a number of these technologies.  The white paper explains why energy is wasted with today’s technologies and how these new memory types can dramatically reduce energy consumption.

It also provides a Continue reading

Micron’s Super-Fast New 32GB NVDIMM

 

Switch TrackMicron Technology has introduced a 32GB NVDIMM-N.  Perhaps the most important thing about this device is not so much its high density as the fact that it runs at higher bus speeds than competing NVDIMMs, doing 2933 megatransfers per second (MT/s), a speed that Micron representatives tell us is required to support Intel’s Skylake processor.

Up to this point NVDIMM-Ns have been limited to 2400 MT/s, which is fast enough for Broadwell, but which misses the mark for Skylake.  Design is tricky even at this slower speed, requiring a number of expensive high-speed multiplexers in the DRAM’s critical speed path.

“Multiplexers?”  Yes, NVDIMMs use them, even though no other kind of DIMM does.  The Memory Guy can explain why, having just finished a report covering the NVDIMM market and technology.

Here’s a little refresher for those who either don’t remember or never knew that NVDIMM-N requires multiplexers.  The NVDIMM-N looks to the system like a standard Continue reading