In this first post of a five-part series contributor Ron Neale analyzes selector technologies presented by CEA Leti at the 2018 IEDM conference last December.
At the close of last year the IEDM maintained its long-standing reputation for offering across-the-board the right focus at the right time on important and key parts of the electronic device discipline. For those with an interest in the future of stacked or 3D NV-memory arrays there were a number of important papers and presentations on a variety of thin film memory selectors or matrix isolation devices (MIDs).
Important, because as the move towards stacked memory arrays for storage class memory (SCM) and persistent memory (PM) applications gains momentum, the thin film selector may be the device which is key in determining the performance and reliability for a number of different types of NV memory arrays or even the very existence of that type of memory array. One of the important and poorly understood variables in the mix is the selector forming voltage and the structural changes which lead from it to the operating device threshold voltage which, in my view needs a lot more by way of detailed understanding.
As the memory array moves into Continue reading “NV Stacked Memory: Selectors and Forming (Part 1)”
