In this post contributor Ron Neale analyzes Weebit Nano’s recently-announced memory array, based on SiO and an Ovonic Threshold Switch selector developed by CEA-Leti in France. Ron employs his extensive background in Ovonic devices to try and sleuth out the characteristics of both the memory element and the selector, and to understand some of the inner workings of the cell.
Weebit-Nano (Hod Hasharon, Israel), have recently reported some first steps on the path they have outlined to meet their bold claim of Continue reading “Weebit-Nano’s First Small Steps on the NV Memory Road”
In this post contributor Ron Neale looks deeper into a paper delivered by CEA-Leti at December’s 2019 IEDM conference, evaluating its fundamental thesis that an OTS selector is suitable for high-density memory arrays. Another interesting aspect of this same paper was the subject of an earlier post.
One eye catcher at IEDM 2019 was a paper from a team in France at CEA-Leti, Minatec, Grenoble, IMEP LAHC CNRS and INL CNRS, INSA Lyon, by D. Alfaro Robayo et al titled: Reliability and Variability of 1S1R OxRAM-OTS for High Density Crossbar Integration. I discussed another aspect of Continue reading “Chalcogenide Selectors and Oxide Memory Move Towards 1Gbit”
Ron Neale returns to The Memory Guy blog to discuss a “Universal Law” about memory elements and selectors that was presented by CEA Leti at the IEEE’s 2019 IEDM conference last December.
At IEDM 2019 D. Alfaro Robayo et al presented a paper titled: Reliability and Variability of 1S1R OxRAM-OTS for High Density Crossbar Integration that had a rather interesting claim of a “Universal Law”. It is possible that some links to the past might help to provide an explanation for Continue reading “Observations on the “Universal Law” for NV Memory Cells”
In this first post of a five-part series contributor Ron Neale analyzes selector technologies presented by CEA Leti at the 2018 IEDM conference last December.
At the close of last year the IEDM maintained its long-standing reputation for offering across-the-board the right focus at the right time on important and key parts of the electronic device discipline. For those with an interest in the future of stacked or 3D NV-memory arrays there were a number of important papers and presentations on a variety of thin film memory selectors or matrix isolation devices (MIDs).
Important, because as the move towards stacked memory arrays for storage class memory (SCM) and persistent memory (PM) applications gains momentum, the thin film selector may be the device which is key in determining the performance and reliability for a number of different types of NV memory arrays or even the very existence of that type of memory array. One of the important and poorly understood variables in the mix is the selector forming voltage and the structural changes which lead from it to the operating device threshold voltage which, in my view needs a lot more by way of detailed understanding.
As the memory array moves into Continue reading “NV Stacked Memory: Selectors and Forming (Part 1)”