At the ISSCC conference last month Kioxia and Sandisk provided more details on the BiCS8 NAND flash chip that the companies will be shipping soon.
BiCS8 is the next generation of the two companies’ jointly-developed 3D NAND technology. Although today’s volume product is very different from Toshiba’s originally-disclosed BiCS process, so far the process changes have largely been incremental improvements. BiCS8 will differ significantly from its predecessors since it will use a hybrid bonding approach to drive 332 layers of bit cells. This post will explain all that.
In March 2023, Western Digital announced that the upcoming BiCS8 process would depart from prior generations by being manufactured on two wafers rather than one. One wafer is used only to manufacture an array of 3D NAND bits, and the other contains the logic which is produced using a standard CMOS logic process. The two wafers are bonded to each other face-to-face in a process the companies refer to as “CBA” for CMOS Bonded to Array.
Here’s a brief visualization I made in 2018 to explain the thinking behind the process.
It’s not too accurate, but it gives you a rough idea of how this technique works. This animation illustrates a 3D NAND chip made with the logic at the left side and the array on the right. The logic is broken off from the chip, flipped over, and mounted on top of the array.
While it would seem that stacked wafers would increase manufacturing costs, since two wafers would be necessary instead of one, and since the die size would be about the same for a CMOS Under Array (CUA) version of the same chip, both companies assured The Memory Guy that this approach would reduce costs, although neither company at that time desired to explain how. The ISSCC presentation gave a glimmer of an insight about this.
Before I get to that insight, though, I should explain that the 2-wafer approach, called Hybrid Bonding, was initially introduced in 2019 by TSMC in China, despite Sandisk and Toshiba claims of its being “Revolutionary.” When YMTC revealed its planned “Xtacking” approach I considered it to be a very rapid way to ramp production with a trade-off that the die would be much more expensive, resulting in a less profitable chip. This made sense, given that YMTC had ample funding and was commissioned to create and grow a Chinese presence in the memory market, but was not required to immediately become profitable, as would be required for other memory start-ups. Even at that time, though, I had heard rumors that mainstream memory makers had explored the two-wafer option for reasons that were not disclosed.
At ISSCC, both the Kioxia/Sandisk JV and Samsung shared information on upcoming chips that would use YMTC’s approach in production.
The Sandisk/Kioxia ISSCC paper presented a 332-layer hybrid-bonded chip that took great advantage of the CMOS logic layer to increase the chip’s I/O speed to 4.8Gb/s through a high-speed 6th generation Toggle DDR interface, all while reducing the chip’s power consumption. They could do this because logic that is built using a standard CMOS logic process performs significantly better than logic that is built using a 3D NAND-compatible process. The speaker hinted that one reason to use standard CMOS logic was that the very high layer count would result in a significantly higher capacitive load on the word lines (the actual layers themselves), and that load can be driven faster and more efficiently by standard CMOS logic. On the other hand, since there are more word lines, a lower percent of them will be selected at any one time, and this allows smaller voltage swings, which the presenter said accelerates the array access by 10%.
One other issue which was not directly stated but that was hinted at, is that the large layer count seems to have caused the logic to be come so complex that a standard CUA (CMOS Under Array) approach would have had to devote a very large area to the logic, and the actual memory bit array didn’t need to be that large. (Logic that is made using a NAND flash process takes up more room than the same logic built on a standard CMOS logic process.) Since memory makers must do everything they can to reduce the die size, then using standard CMOS logic to reduce the overall die size could result in a less costly chip, despite the fact that it took two wafers to produce.
Now we have an answer about why everyone seems to be intent on moving to a bonded-wafer approach sometime in the future. YMTC will naturally have a lot more learning, since the company has been using a bonded wafer process for five years, and that will be to the company’s advantage, but memory makers are very disciplined at ramping new technologies, so others are likely to become proficient at the bonded wafer process pretty quickly.
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Oh, and about that graphic: It’s part of the first figure in the Kioxia/Sandisk ISSCC 2025 paper, which can be purchased from the IEEE. It illustrates the two dice, the memory array on the top, face-down, and the logic chip on the bottom, face-up, as if someone had been able to pry them apart. In real life it would be very difficult even to tell that two chips had been used to create the structure, although the chip would be twice as thick as any other 3D NAND die. For 3D NAND, the layers, no matter how many there are, are significantly thinner than the wafer itself.