Applied’s Take on 3D NAND

Applied Materials expects for 3D NAND to grow the etch & CVD markets by 50%Early this month I was invited to participate in Applied Materials’ (AMAT) Analyst Day.  The sessions were rich in data covering the markets that would profit the company over the next few years.

Naturally, The Memory Guy fixated on those presentations that dealt with memory.  When it came to the upcoming transition to 3D NAND, AMAT had a lot to say.

A later post will explain what 3D NAND actually is.  Suffice it to say that today’s approach to making NAND flash has nearly reached its limit, and the approach that manufacturers plan to use in the future involves making NAND strings that stand on their ends.  This has phenomenal implications on Continue reading “Applied’s Take on 3D NAND”

SanDisk & Toshiba Move to Next Process Node

SanDisk's explanation of old vs new 19nm processesSanDisk and Toshiba, in separate announcements, both today disclosed their next-generation process technology.

The companies introduced their new “1y” processing node that, according to SanDisk, produces 19nm x 19.5nm cell, versus the earlier “19nm” process (or “1x”) that used a 19nm x 26nm cell.

The graphic for this post (click to enlarge) was presented during SanDisk’s May 5th Analyst Day and compares the 24nm process to the 19 x 26nm process, moving to the 19 x 19nm process, and eventually to “1z” which neither company is yet revealing.  After the 1z process SanDisk believes Continue reading “SanDisk & Toshiba Move to Next Process Node”

Hybrid Memory Cube Making Progress

Conceptual Cutaway Drawing of the Hybrid Memory CubeOn Tuesday the HMC Consortium (that’s short for “Hybrid Memory Cube”) announced that members have agreed upon a specification.  The consortium has been moving rapidly, meeting its targets despite the revolutionary nature of the interface.

As a reminder, this technology stacks multiple DRAMs in a single package with a logic chip at the base of the stack that performs all the signalling to the rest of the system.  Signals between the DRAMs and logic chip use through-silicon vias (TSVs) as interconnections.  This allows the technology to deliver 15 times the performance of DDR3 at only 30% of the power consumption.  The Memory Guy first posted about the HMC in late 2011.

The consortium explains that the HMC interface already has 100 adopters, and that a few Continue reading “Hybrid Memory Cube Making Progress”

Macronix Solves Flash Wear Problem

Macronix Headquarters, Hsinchu TaiwanThe December issue of the IEEE Spectrum includes a fascinating article about a 100 million cycle flash memory developed by Macronix.  The company will present this design at at IEDM this month.

In brief: Macronix’ researchers buried a heater in the array to heat the tunnel dielectric, annealing out the disruptions & traps that might cause a bit to fail.

A prototype has so far been tested more than 100 million cycles and it shows no sign of impending failure.  Researchers believe that it is likely to reach one billion or more cycles, but such testing will take several months.  This just may be able to Continue reading “Macronix Solves Flash Wear Problem”

Spansion Introduces 8Gb NOR Flash

Just in case anyone thought that NOR flash was not going to get any denser, Spansion announced a single-chip 8Gb parallel NOR today.  This product, built using Spansion’s MirrorBit technology on a 45nm line is not only the densest monolithic NOR chip on the market, it’s also the NOR flash with the finest process technology.

Spansion’s GL-T product is aimed at applications that need high densities at read speeds faster than those that NAND flash can deliver.  Spansion tells The Memory Guy that read performance is 95MB/s and program performance is 1.8 MB/s.

Sampling will commence in December, with production in the first quarter of 2013.

Hynix and Spansion Join Forces

Spansion and SK Hynix AllianceSK Hynix and Spansion have announced a strategic NAND alliance under which Hynix will serve as a foundry for low-density SLC NAND chips made for Spansion using Hynix’ advanced processing nodes.

These products, aimed at the embedded market, should serve to strengthen Spansion in a market in which the company thrives. In fact,  Spansion expressed this very well in their press release, citing: “Spansion’s recognized customer support and commitment for longevity of supply, which is highly valued in the embedded market, where Spansion has established relationships.”

The new chips will be manufactured in “4x, 3x, and 2xnm” process technologies.

The companies have also agreed to cross-license their patent portfolios.

You may be asking yourself: “What does Hynix Continue reading “Hynix and Spansion Join Forces”

Remembering Core Memory

Ryszard Milewicz' photo of Core MemoryNostalgia buffs who lived through computing in the 1970s will enjoy some magnificent photos shared in a blog post by Ryszard Milewicz.  These photos give three views of a ferrite core memory plane.  The photo from this blog is a part of one of Mr. Milewicz’ close-up photos.

For those who were not exposed to core memory, this technology was based upon an approach in which every individual bit of a computer’s memory was a tiny donut made of compressed iron powder (“Ferrite”) that had to be hand strung with copper wire into a plane of bits.

A co-worker of The Memory Guy once had a high-speed core memory array that he used as Continue reading “Remembering Core Memory”

NAND SSD Performance to Decline over Time

Chart from the Grupp, Davis, Swanson paper showing latency increases with capacityA few articles at ComputerworldTom’s Hardware, and The Verge were recently passed my way.  These reported on a paper presented at last week’s USENIX conference that predicted how NAND flash’s future performance declines would impact tomorrow’s SSDs.

The paper found that SSD performance is likely to decrease over time as SSDs increase in capacity.  The report postulates that SSDs of the future: “may be too slow and unreliable to be competitive against disks of similar cost in enterprise applications.”

Sadly, the Tom’s Hardware and Verge articles focused more on one of the assumptions behind the paper Continue reading “NAND SSD Performance to Decline over Time”

WIOMING: Another Spin on the Hybrid Memory Cube

ST-Ericsson & CEA-Leti WIOMING Multichip ModuleAt a Conference in San Francisco today (Tuesday December 13 ) ST-Ericsson and CEA-Leti presented a paper on something the companies called a: “Breakthrough 3DIC with Wide I/O Interface.”

This product appears to be a variation on the Hybrid Memory Cube, or HMC concept detailed in a prior post.

Remember that the HMC stacks a number of DRAM chips atop a logic chip.  The memories store data and communicate to the logic chip through thousands of through-silicon vias (TSVs) while the logic chip handles communications with the outside world. Continue reading “WIOMING: Another Spin on the Hybrid Memory Cube”

Micron, Intel, Introduce 128Gb NAND Chip

IMFT 20nm NAND Flash DieMicron Technology and Intel announced today (6 December, 2011) that the two companies are sampling a 128 gigabit (that’s 16 gigabytes) NAND flash chip manufactured by the company’s IMFT joint venture.

This is a doubling of the capacity of the 64Gb chip the companies announced in April, but they assure us that the size of the die hasn’t doubled, and the accompanying photo supports this.  Intel tells us that the die will fit into standard BGA and TSOP packages. Continue reading “Micron, Intel, Introduce 128Gb NAND Chip”