Vertical Structures - The Memory Guy Blog

New Book: Vertical 3D Memory Technologies

Wiley has recently published a new book by Betty Prince titled Vertical 3D NAND Technologies that is one to consider if you want to bring yourself up to speed on recent research behind today’s and tomorrow’s 3D memory technologies.

For those who haven’t previously encountered Dr. Prince, she is the author of a number of key books covering memory design and holds memory patents written over her 30-year career in the field.

The book provides capsule summaries of over 360 papers and articles from scholarly journals on the subject of 3D memories, including DRAM, NAND flash, and stacked chips.

These papers are organized into Continue reading “New Book: Vertical 3D Memory Technologies”

Making 3D NAND Flash – Animated Video

The good people at Coventor have graciously allowed me to post their video of the Pipe-Shaped BiCS 3D NAND flash process onto The Memory Guy blog site. Click the image to see it play out.

Coventor tells me that they are the leading Continue reading “Making 3D NAND Flash – Animated Video”

Samsung Begins Operations at its Xi’an Fab

Samsung has announced that the company’s newest memory fabrication plant (Fab) in Xi’an, China has “begun full-scale production operations”, adding that: “The new facility will manufacture Samsung’s advanced NAND flash memory chips: 3D V-NAND.”

I immediately asked whether the plant will build products other than 3D NAND, and the company has replied that this will be the only product produced in the Xi’an plant. What Samsung has not said is what is meant by “full-scale production operations.” Typically wafer fabs start with a very low production capacity as new tools are being qualified, only ramping to high-volume production a year or more after initial production.

Samsung points out that production has begun a mere 20 months after initial groundbreaking, which is quite Continue reading “Samsung Begins Operations at its Xi’an Fab”

Comparing Samsung V-NAND to Micron 16nm Planar NAND

I was recently directed to a very interesting blog post written by 3D technologist Andrew Walker of Schiltron in which he compares two NAND flash chips that were presented at the IEEE International Solid State Circuits Conference (ISSCC) on February 12.

The post, titled Samsung’s V-NAND Flash at the 2014 ISSCC: Ye Distant Spires… is on the 3D InCites website.

Dr. Walker puts a lot more time and effort into his graphic representations of 3D NAND chips than do others (The Memory Guy included) and this makes it much easier to understand the issues he points out. He shows us that Samsung’s 3D NAND cell is about 5 times the size of a 40nm planar NAND cell and about 30 times that of Micron’s 16nm planar cell, and that the 3D NAND’s physical area is unlikely to change with any future 3D technology generations.

For this and other reasons (given in the article) he states that the Samsung V-NAND is “an impressive achievement but not a realistic foundation for the future.”

After having compiled my series on 3D NAND I can appreciate Dr. Walker’s opinion. This is certainly going to be a difficult technology to master, and it could be quite some time before the cost structure for 3D NAND can compete against that of today’s planar technologies.

Give the Walker post a quick read and judge for yourself whether we are at the brink of a 3D conversion or if this technology can be expected to slip out a few years.

Why NAND is So Difficult to Scale

NAND flash is the process leader in memory technology, and this puts it in a very challenging position: It must ramp to high volume production using techniques that have never been tried before.

The graphic for this post (click to enlarge), supplied by ASML, the semiconductor industry’s leading lithography tool supplier, illustrates the challenge of migrating from one process node to the next. Across the bottom, on the X-axis, are representative process nodes ranging from “2D-45”, or two-dimensional (planar) 45nm NAND, to “3D-5x”, or three-dimensional 5xnm NAND. Below these numbers are the year of volume production.

The vertical axis, labeled “Tolerance” represents the minimum Continue reading “Why NAND is So Difficult to Scale”

What is a “Multilayer Cell”?

From time to time I get questions from investors in the memory business asking: “What is a multilayer cell?”

The answer is: “There is no such thing: It’s a misstatement.”

The term “MLC” has, by a number of people, been mistranslated to “multi-layer cell.” The misunderstanding appears to have originated in the financial community. People in the flash memory business never use the term at all.

Yes, we talk about MLC, but to us the term means “multilevel cell”.

A multilevel cell is a cell that uses varying voltage levels to represent different states. With four voltage levels the resulting four states on a single cell can be turned into Continue reading “What is a “Multilayer Cell”?”

Samsung’s View on Charge Trap Flash

At the Flash Memory Summit yesterday ES Jung, PhD, EVP & GM for the Samsung R&D Center, explained the inner workings of Samsung’s new V-NAND vertical NAND flash technology. I will shortly be writing a series to explain what a 3D NAND is since there is little on the web that gives clear details about the technology.

One key attribute of most 3D NAND approaches is the use of a charge trapping layer. This has to do with the difficulty of manufacturing sideways floating gates.

Dr Jung delighted the show’s audience by explaining that a standard floating gate is like Continue reading “Samsung’s View on Charge Trap Flash”

Samsung Announces 3D NAND Production

Samsung has announced production of its 3D NAND technology. This approach, first introduced by Toshiba in 2007, allows NAND flash makers to achieve more bits per chip by building NAND strings, which normally run across the surface of the chip, as vertical stacks.

It’s a fascinating technology, since it harnesses exotic steps invented by DRAM makers in the 1990s to get over scaling problems in that technology. At the time DRAM had to go vertical to follow Moore’s Law and there were two schools of vertical DRAM: Stacked Capacitor, and Trench Cell. The stacked capacitor camp layered polysilicon and silicon dioxide into layers to form a vertical capacitor. The trench camp etched a very narrow and deep hole into the silicon and lined it with the capacitor plates. Both worked very well, but over time the trench makers have Continue reading “Samsung Announces 3D NAND Production”

Applied’s Take on 3D NAND

Early this month I was invited to participate in Applied Materials’ (AMAT) Analyst Day. The sessions were rich in data covering the markets that would profit the company over the next few years.

Naturally, The Memory Guy fixated on those presentations that dealt with memory. When it came to the upcoming transition to 3D NAND, AMAT had a lot to say.

A later post will explain what 3D NAND actually is. Suffice it to say that today’s approach to making NAND flash has nearly reached its limit, and the approach that manufacturers plan to use in the future involves making NAND strings that stand on their ends. This has phenomenal implications on Continue reading “Applied’s Take on 3D NAND”

Hynix and Spansion Join Forces

SK Hynix and Spansion have announced a strategic NAND alliance under which Hynix will serve as a foundry for low-density SLC NAND chips made for Spansion using Hynix’ advanced processing nodes.

These products, aimed at the embedded market, should serve to strengthen Spansion in a market in which the company thrives. In fact, Spansion expressed this very well in their press release, citing: “Spansion’s recognized customer support and commitment for longevity of supply, which is highly valued in the embedded market, where Spansion has established relationships.”

The new chips will be manufactured in “4x, 3x, and 2xnm” process technologies.

The companies have also agreed to cross-license their patent portfolios.

You may be asking yourself: “What does Hynix Continue reading “Hynix and Spansion Join Forces”