How Samsung Will Improve 3D NAND Costs

One of the most intriguing revelations during the Flash Memory Summit two weeks ago was Samsung’s new approach to stairstep etch in 3D NAND.  This was one of numerous innovations the company’s  EVP of Flash Products & Technologies, Kye Hyun (KH) Kyung, shared during Samsung’s Tuesday Morning keynote presentation.

The Memory Guy would point readers to the pdf of Samsung’s presentation on the Flash Memory Summit website, but it isn’t there, and it’s unlikely to ever be posted there.  Samsung seems to have a policy that prohibits sharing such presentations.

Although I was unable to get a copy of the drawing that the keynoter used, I have tried to re-create it using, of all things, Excel!  The result is the graphic for this blog post.  The only thing I was unable to easily recreate was the different colors representing the layers of the 3D NAND.  You’ll need to use your imagination and envision layers of two colors, with all the surfaces exposed on the top being the same color, but at different layers of a 64-layer structure.

Today’s common approach to 3D NAND’s stairstep is to etch a simple step pattern in one dimension, which I illustrated in an early 3D NAND blog post four years ago.  This is a challenging process because it theoretically can be done using only one litho step followed by a series of vertical and horizontal “Pull-Back” etch steps.  That process has eluded the industry so far, forcing manufacturers to perform multiple lithography steps, each of which adds cost to the wafer.  Additionally, the more layers the wafer uses, the larger of an area is consumed by the stairs.  This means that a 64-layer NAND die must necessarily be larger than its 32-layer counterpart.

Samsung’s new SSDP or Stair Step Dividing Pattern both reduces lithography steps and shrinks the die area consumed by the staircase.  It’s based on making the stairs two-dimensional, rather than one-dimensional.  Here’s how it appears to be made:

First, four long steps are etched in the right-to-left direction of the figure.  This is probably done using a pullback etch series based on a single litho step, similar to the original approach, but two layers (rather than one) would be  etched at a time.  This is done on both the front of the feature and the back simultaneously, giving the pattern that “Up and Down” shape.

This, by itself, would expose the same layers on each step for both the front and the back, so another litho/etch step would be used to lower all of the steps on the far side by one layer to offset everything.  At the end of all of this the top eight wordline layers would be exposed.

After this the process changes direction and is rotated 90 degrees.  Eight steps would be etched from the right side of the diagram to the left.  Each  step is etched eight layers deep, exposing layers below the eight layers of the original “Up & Down” staircase to the left.

It’s really a very clever approach.  Ideally this would require only three lithography steps and 4+1+8 = 13 etch steps.  The entire pattern should only consume 1/8th the die area of a more conventional staircase.  The standard approach, while it would ideally require only one lithographic step, would need 64 etch steps and would consume eight times the die area.

In this way Samsung has reduced the die size of its 64-layer NAND while reducing process complexity and cost.  This approach is really the best of both worlds!

Readers who are interested in the 3D NAND market, including in-depth knowledge of the technologies and a very sound understanding of how the market dynamics will cause today’s shortage to transition into an oversupply are welcome to approach Objective Analysis.  It is our passion to assist our partners to make the best business decisions by helping them understand what to expect, when to expect it, and why it will happen.  Please contact us to explore ways we can provide your company with a strong competitive advantage.