I recently received a request for comment on an article in Tom’s Hardware titled Samsung touts 96% lower-power NAND design – researchers investigate design based on ferroelectric transistors. It sounded pretty compelling, so I did a little investigating.
The Tom’s Hardware piece was based on a Nov 26 Nature article titled Ferroelectric transistors for low-power NAND flash memory. The Nature article details a demonstration of a transistor that could be beneficial to NAND flash, that researchers built into both planar and 3D NAND strings on a very small scale.
It’s an interesting combination of a couple of popular research topics:
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- Reducing the NAND string’s channel resistance by either crystallizing the polysilicon (SILC) or by replacing it with an oxide like IGZO
- Adding a ferroelectric layer to the wordline/channel interface. Intel and (I think) imec have prototyped 3D DRAMs based on this structure.
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The Memory Guy has been a longtime fan of ferroelectrics. They offer a lot of technical benefits. I freely admit, though, that it doesn’t matter whether or not a technology excites me when it comes to commercial success. A good example of this is Intel’s 3D XPoint/Optane experiment, which never took off because it never reached the required production volume to get its costs aligned with DRAM. It’s all about the economies of scale.
Interestingly enough, ferroelectrics aren’t only being researched for FRAM, which is deeply covered in the Objective Analysis/Coughlin Associates New Memory Report. Ferroelectrics have also been shown to help shrink the capacitor in DRAMs, due to their very high dielectric constant, and the Samsung paper proves that they are a good substitute for the charge trap that is currently used in every NAND flash bit cell.
It will be interesting to see whether Samsung’s research project makes it into production. Hafnium-based ferroelectrics have been a long time coming!