NV Stacked Memory: Selectors and Forming (Part 1)

Ron NealeContributor Ron Neale analyzes selector technologies presented by CEA Leti at the 2018 IEDM conference last December.

At the close of last year the IEDM maintained its long-standing reputation for offering across-the-board the right focus at the right time on important and key parts of the electronic device discipline.   For those with an interest in the future of stacked or 3D NV-memory arrays there were a number of important papers and presentations on a variety of thin film memory selectors or matrix isolation devices (MIDs).

Important, because as the move towards stacked memory arrays for storage class memory (SCM) and persistent  memory (PM) applications gains momentum, the thin film selector may be the device which is key in determining the performance and reliability for a number of different types of NV memory arrays or even the very existence of that type of memory array.  One of the important and poorly understood variables in the mix is the selector forming voltage and the structural changes which lead from it to the operating device threshold voltage which, in my view needs a lot more by way of detailed understanding.

As the memory array moves into three dimensions it also moves away from the comfort zone of the relatively easy access to devices that are on the silicon surface. Diodes or transistors no longer can be used as selector options, so the sensible selector option of choice becomes a threshold switching device. Other non-linear devices are also an option and in some cases the selector can be possibly even be the non-linear conduction characteristics of the memory device itself.  An additional important point is that many thin film memory devices ReRAMs and CbRAMs require bidirectional current or voltage for write and erase.

Although chalcogenide-based PCM memory devices can be and usually are operated with only a unidirectional current, recent work suggests the endurance will be improved if they too are switched using the first and third quadrant of the I-V characteristics of a threshold switch.

At IEDM Leti/CEA set out their impressive memory and technology stall with a memory workshop the evening before the IEDM conference and a session paper during IEDM itself titled: Optimized Reading Window for Crossbar Arrays Thanks to Ge-Se-Sb-N based OTS Selectors (A. Verdy et al, CEA Leti MINATEC, Proceedings, IEDM 2018).  In her workshop presentation Leti’s Dr. Marie-Clare Cyrille, Director of Technical Marketing Strategy for Advanced Computing, who was also a co-author of Leti’s session papers on selectors, covered many NV-memory related topics and attempted to bring some order to those trying to assess the relative merits of the different memory selector options.

One of her slides provided a view of the relative performance of three important attributes for selectors of different compositions in a table reproduced below.  Along the way she highlighted the success the Leti/CEA/MINATEC team had in engineering and optimising a GeSbSeN (GSSN) composition selector, claiming they have achieved the optimum in selector performance especially with respect to pre-switching leakage, an essential for large memory arrays.  This is the highlighted column below.


Doped Chalco-genide







Integration or Device Annealing temperature


120 mins


30 mins


30 mins



30 mins


30 mins

Leakage Current @ Threshold Voltage Vt/2 (A)







Endurance Switching cycles







(After Marie-Claire Cyrille, Leti Memory Workshop, IEDM 2018)

This table introduces the important selector-based fabrication variables of annealing time and temperature.  Those are the times and temperatures which, after deposition, the selector film must withstand to obtain the desired results.  Those who follow chalcogenide memory will know that annealing, even at room temperature, increases the off state resistance and threshold voltage, usually described as drift, resulting in a problem with some operation protocols.

Not only was Leti able to improve structural integrity, based on some brilliant and careful analysis of bonding structures during all conditions of the doping and engineering of GeSbSe (GSS) and GeSbSeN (GSSN) based selectors described in the paper, but the organization was also able to link atomic structure to key electrical characteristics. Their examination of Raman spectra and the Ge-N absorption band, indicates that after the film is deposited the nitrogen doping atoms are spread randomly through the film.  Annealing for 30 minutes at 400° C homogenizes the structure with the formation of a Ge-Nx bonds.

A summary of their detailed structural analysis showed that while homopolar Sb-Sb and Se-Se bonds were undesirable, Ge-Se and Sb-Se bonds were most beneficial.  The formation of these beneficial bonds required the correct level of Sb and nitrogen doping.

Variations in composition were used to address the problem of the high and unacceptable forming voltage, which Leti calls “Fire” voltage.  Chalcogenide based memory devices also have a forming voltage if fabricated in the amorphous state. Forming voltage is not seen as a problem or even discussed much in polite circles, even less so when berating ReRAMs because of the need for forming in those devices.  The reason for this is that chalcogenide memory devices are usually fabricated in the crystallized or conducting state and only the lower operating threshold voltage is ever involved in device operation.  However selectors must be fabricated in the high resistance state and hopefully they will stay in that state forever.

Five parameters must be optimized to make a selector suitable for large SCM arrays:

  1. Forming threshold voltage;
  2. Operating threshold voltage;
  3. Forming leakage current;
  4. Operating leakage current
  5. Holding current.

To simplify things and illustrate the difference between the forming and operating voltages I have reproduced below the essential elements of a more detailed figure from the Leti presentation.

Selector Characteristics

With the need for forming the picture which now emerges for the fabrication of the selector is a fabrication sequence which, as a parody of an old teaching adage runs: you make it, you makes it again and then you makes it again. Or in more formal language: you deposit the film, you anneal it to homogenize it, and then you form it.

The Leti/CEA paper attacked the problem of understanding what happens during annealing and the result on the important selector characteristics from variations in composition for the GeSbSe (GSS) glasses when doped with nitrogen and from variations in Sb content.

The problem with GSS and GeSe alloys is while they have a number of properties which would make them a good choice as selectors, they suffer from unacceptable high forming and operating threshold voltages and structural instability.

By a combination of the correct choice of nitrogen doping and Sb content a minimum and acceptable value of both forming voltage and operating voltage was achieved.  With 20% Sb and with the N doping level remaining a proprietary secret the threshold voltage was reduced to 2.25 Volts and the forming voltage to 3.75 Volts, for a difference of 1.5 Volts.

It is interesting to speculate what the forming process might involve at a molecular level.  If the ratio between the forming voltage and operating voltage is constant as a function of thickness then it would suggest that the whole body of the film has been modified in some way.  If, however, it is independent of film thickness then it opens up a number of possibilities for example:

  • Some metal-amorphous semiconductor interface junctions have been destroyed;
  • Some material has crystallized somewhere in the film
  • A high resistance nano-filamentary region has formed from which the conducting filament expands after switching.

The Leti paper explored two rules for the read operation. The first relates to the relative values of the threshold voltages of the two devices in the memory cell, i.e the memory and the selector.  One with the threshold voltage of the selector higher than that of the memory, with the other the opposite case.  With a second rule, in order to avoid the possibility of PCM disturb, the memory device must not switch when in its high resistance state during the read operation.

PCM Bit CellIn simple terms from a circuit viewpoint the two devices in the memory cell can be considered as one acting as the resistive load for the other, and a load line can be used to analyse the circuit.  I will do that using the color conventions shown above: Blue represents the PCM memory element, and red denotes the selector in a crosspoint array.

In the following figure I have sketched two examples of how the load lines for the PCM in its Reset state (the blue curves) are used to define the upper and lower voltage limits of the memory read window, denoted by the green arrows.  For each voltage the stable settling point of the circuit is marked with the yellow dot markers.  The read voltage would be positioned as the mid point between these two limits, and is marked by the red arrow on the voltage axis.

Read Window

Any attempt to increase the width of the read window by increasing the voltage beyond the upper limit would cause the selector’s current to exceed its threshold switching current (with the yellow dot moving into the dashed part of the red curve) and the selector would switch.  Switching of the selector should be avoided as it would bring with it the potential of read disturb of the PCM and an erroneous read current.  The width of the read window is designed to deal with all the variables associated with effects of temperature and other array design variables.

In the figure below I have sketched the problem which occurs when the PCM is in its unformed “As-Fabricated” state; here the purple curve illustrates the pre-threshold switching characteristics of the selector in its unformed state with a higher “fire” or forming threshold voltage, while the red curve shows the behaviour of a formed selector as was used in the illustration above.  This figure also includes the same blue PCM load line (the blue curve) for the PCM in its Reset state as was used in the above figure; in this illustration the blue line has been moved to a position with the read voltage Vr applied.  To complete the picture for both memory states, the same graph now includes the black curve for the PCM in its Set, or low-resistance state.  Note that I have used the same voltages as used for a similar example in the Leti paper: The threshold voltage of the selector is 1.5 Volts and the read voltage 3 Volts with a difference between the forming voltage and the operating voltage of 1.5 volts.

Set, Reset, and Forming

The two green marker dots would be the two read current or voltage levels for normal operation when reading the two different data states of the PCM, the lower series resistance of the Set memory cell would have caused the selector to have switched resulting in the higher current, the upper green marker.

Now what becomes clear from this figure and the purple curve representing the selector’s unformed state is that the application of the read pulse does not allow the Set state of the PCM to be detected.  The currents of the settling points for both PCM memory states, the two black marker dots, are almost indistinguishable.  The obvious simple step of increasing the width of the read window brings with it the problem of the unwanted switching of the selector and the associated read disturb problems.

While it might be possible to deal with this situation with respect to write, it will preclude any of the write-time and endurance-saving read-before-write protocols because any unformed selectors would always give a HRS (high-resistance state) result for a memory in its as fabricated low-resistance state.

The seemingly obvious solution would be to reduce the thickness of the selector in order to reduce both the forming and operating threshold voltages, but such a move carries with it the unwanted penalty of increased leakage current.

The only solution offered by Leti to any read problems associated with forming was to minimize the forming voltage. At the other end of the scale for selectors, during the same IEDM session, An Chen of the IBM Research Division explored large crossbar array modelling with nonlinear selectors in his paper: A highly Efficient and Scalable Model for Crossbar Arrays with Non-linear Selectors (An Chen, IBM Research Division, San Jose, Proceedings, IEDM 2018).  I raised with him the reason why he also had not dealt with, or mentioned, any problems with selector forming.  He replied by email:

My paper addresses a general modelling approach for non-linear selectors (including threshold switching type). Although not all volatile switching selectors require forming, it’s a very good point that forming is observed in some reported OTS-based selectors. The calculation presented in my paper did not specifically address forming, but the model can handle forming step as well. It is straightforward to describe selectors in the forming step with electrical parameters different from the following cycles for the purpose of crossbar array modelling. The crossbar array circuit requirements would be affected by forming, since different device parameters are involved in the first and later cycles. Depending on how much difference exists, forming could present a difficult challenge. Small difference may be tolerated within operation margin, but large difference needs to be handled carefully in the circuit design and operation methods.

It might be a case of Western Digital and Aachen University to the rescue. Their presentation at IEDM, titled: Forming free Mott-Oxide threshold selector nanodevice  showing S type NDR with high endurance (10^12 cycles), excellent Vth stability (<5% ), fast (<10ns) switching and promising scaling properties (T. Hennen et. al., Aachen University & Western Digital, Proceedings, IEDM 2018), offered a forming free (V(1-x) Cr x)2 O3 composition thin film selector device with region of stable post-threshold switching negative resistance in its I-V characteristics.  These were large area (250 x 250 nm) devices with an upper platinum electrode.  The presentation made some impressive claims of 10ns switching time, endurance of 1010 switching cycles and excellent threshold voltage stability.

It was established that thermal effects accounted for the threshold switching with temperatures of 350°K and 500°K at the threshold and conducting states respectively.  Simulations suggested the high leakage current could be reduced with scaling.

The Aachen University Western Digital team did offer some help with a possible explanation of forming.  This was in relation to the ability, under certain operating conditions, for the VCrO devices to be use as a one-time-programmable non-volatile memory with two different threshold voltages as the memory state.  The researchers suggested that a filamentary high-resistance conduction path could be responsible for the lower threshold state by acting as the initiating point from which the post-threshold switching conducting state can expand radially.

Perhaps (and what I hope) my comments here will do is promote some grad student or even Leti/CEA/MINATEC or IBM to investigate the relationship between selector forming voltage and device thickness and uncover what is happening structurally to find out if it is a bulk effect, a surface effect, or even the formation of an initiating or filamentary structural change.  The lack of a clear understanding of how selectors are formed may limit the reliability and endurance of these devices.  Possibly this will be something to look forward to at IEDM 2019.

If it was possible to understand what actually happens during the forming of a selector, and a means of reversing it, then it might be possible to utilise a threshold switch as a memory device.  The two different threshold voltages would then be the memory states and possibly eliminate the need for a high current reset pulse or even a selector.

The sting in the tail is Intel with their 3XPoint and Optane products must have solved or engineered around any forming problems associated with their arsenic doped GST threshold switch.  Or it would appear so as my family computer with an Optane memory does not have any problems when any new parts of the memory are utilised.  With a controller on-board it might be possible to implement a stealthy rolling look-ahead write scheme which deals with any selector forming problems as each new area of the memory is or will be needed.  With respect to Optane consideration must be given to the possibility that the poor calculated cell endurance, compared with what might be expected, might have at its roots some compromise related to selector forming.

In my next post I will explore the problem of the “Hows” and “Whys” of selector endurance and its assessment.

Leave a Reply

Your email address will not be published. Required fields are marked *

This site uses Akismet to reduce spam. Learn how your comment data is processed.