What is a Content-Addressable Memory (CAM)? The Memory Guy decided to post this after having recently run across a very strange web post HERE that erroneously inferred that CAM chips from NEC could be a threat to NAND-based SSDs. The article was based on a press release from NEC and Tohoku University that can be read HERE.
It’s not at all surprising that the release was misunderstood – it’s very awkwardly written:
The new CAM utilizes the vertical magnetization of vertical domain wall elements in reaction to magnetic substances in order to enable data that is processing within the CAM to be stored on a circuit without using power.
Continue reading “What is a Content-Addressable Memory (CAM)?”
I got a phone call yesterday from Russell Fish of Venray Technology. He wanted to talk about how and why computer architecture is destined for a change.
I will disclose right up front that he and I were college classmates. Even so, I will do my best to give the unbiased viewpoint that my clients expect of me.
Russell is tormented by an affliction that troubles many of us in technology: We see the direction that technology is headed, then we consider what makes sense, and we can’t tolerate any conflicts between the two.
In Russell’s case, the problem is the memory/processor speed bottleneck.
Continue reading “A Change to Computing Architecture?”
Micron Technology and Intel announced today (6 December, 2011) that the two companies are sampling a 128 gigabit (that’s 16 gigabytes) NAND flash chip manufactured by the company’s IMFT joint venture.
This is a doubling of the capacity of the 64Gb chip the companies announced in April, but they assure us that the size of the die hasn’t doubled, and the accompanying photo supports this. Intel tells us that the die will fit into standard BGA and TSOP packages. Continue reading “Micron, Intel, Introduce 128Gb NAND Chip”
In a December 1 press release IBM announced that the company will be manufacturing Micron Technology’s Hybrid Memory Cube (HMC) which IBM claims to be “the first commercial CMOS manufacturing technology to employ through-silicon vias (TSVs).”
This device is one that Altera, Intel, Micron, Open Silicon, Samsung, and Xilinx have all presented recently as a plausible solution to the difficulty of increasing the speed of DRAM/processor communications. The Hybrid Memory Cube Consortium (HMCC) website offers a deep dive into the details of the consortium and the technology.
Continue reading “IBM to Build Micron Hybrid Memory Cube”
Welcome to “The Memory Guy” the Objective Analysis blog about the world of semiconductor memory chips.
Our goal is to discuss all memory chips, both big and small, that are so prevalent in our electronic accessories. We hope to do that while keeping things brief, light, understandable, and entertaining. Technologies we’ll cover include DRAM, NAND flash, SRAM, NOR flash, EPROM, EEPROM, mask ROM, and all other forms of memory.
Continue reading “Welcome to The Memory Guy – A Blog about Memory Chips”
During the Flash Memory Summit in August three panelists were asked to tell what they thought would be the top ten trends for NAND flash in 2012.
The panelists were:
- Troy Winslow, director of product and channel marketing for the Intel NAND group
- Radoslav Danilak, SandForce founder and now CEO of StorCloud
Here are mine:
- Enterprise SSDs will be used in all data centers
- There is still a lot of growth in NAND
- Controllers will get more sophisticated
- System software will be designed for NAND first
- Tablet PCs will morph into newer devices
- Not everyone can be a successful SSD supplier
- NOR has a long future in code storage
- NAND in PCs is a threat to DRAM, not HDDs
- The death of flash is not imminent
- SSDs in PCs will lose out to NAND + HDD
Over ten future posts I will elaborate on these. As I do I will add hot links to the list above to guide readers to these predictions. If any of the hot links are inactive, come back later and check again.
Many are detailed in reports on the Objective Analysis Reports page.