Crossbar, Inc. has come out of stealth mode with a fascinating new alternative memory technology. Furthermore, the company says that a working memory array has been produced at a commercial fab.
Crossbar says that the technology can put a terabyte onto a single chip. The company has already measured filaments as thin as 6nm, and is confident that it can be shrunk further and that it will support multilevel cells.
Crossbar’s device is a silver filament ReRAM with a difference. For one, the silver filaments are in standard silicon dioxide, probably the most Continue reading “Crossbar’s Radical New Memory Technology”
Micron has announced that it is sampling a new 128Gb NAND flash chip based upon a 16nm process, with production slated for the fourth quarter. To The Memory Guy’s knowledge this is the tightest process available.
The company, with its partner Intel, gained a lead with its 20nm process generation through its use of a Hi-k tunnel dielectric, a new material that replaces more conventional silicon dioxide layer with a new material (Micron won’t say what) that yields the same capacitance with a thinner layer. This has become very important with today’s tight processes because of issues of inter-cell interference.
Other NAND makers are migrating to Continue reading “Micron NAND Reaches 16nm”
Early this month I was invited to participate in Applied Materials’ (AMAT) Analyst Day. The sessions were rich in data covering the markets that would profit the company over the next few years.
Naturally, The Memory Guy fixated on those presentations that dealt with memory. When it came to the upcoming transition to 3D NAND, AMAT had a lot to say.
A later post will explain what 3D NAND actually is. Suffice it to say that today’s approach to making NAND flash has nearly reached its limit, and the approach that manufacturers plan to use in the future involves making NAND strings that stand on their ends. This has phenomenal implications on Continue reading “Applied’s Take on 3D NAND”
SanDisk today announced that its joint venture with Toshiba would begin construction in August of its Fab 5 “phase two” shell. Completion of this Yokkaichi, Japan wafer fabrication facility is slated for mid-2014.
SanDisk expects to use this facility for technology transitions of existing Yokkaichi wafer capacity. The new clean room will provide the space for the additional equipment necessary to transition existing wafer capacity to next-generation 2D NAND technologies and to early generations of 3D NAND technology. In this way it will perform support for Fab 3, Fab 4 and phase one of Fab 5.
This is consistent with the JV’s use of Continue reading “SanDisk & Toshiba to Add NAND Capacity”
SanDisk and Toshiba, in separate announcements, both today disclosed their next-generation process technology.
The companies introduced their new “1y” processing node that, according to SanDisk, produces 19nm x 19.5nm cell, versus the earlier “19nm” process (or “1x”) that used a 19nm x 26nm cell.
The graphic for this post (click to enlarge) was presented during SanDisk’s May 5th Analyst Day and compares the 24nm process to the 19 x 26nm process, moving to the 19 x 19nm process, and eventually to “1z” which neither company is yet revealing. After the 1z process SanDisk believes Continue reading “SanDisk & Toshiba Move to Next Process Node”
There are some who still believe that Toshiba made good on its announcement to cut NAND flash production by 30%. Let’s take a close look to see if that really happened.
Readers may recall that Toshiba stated last July that it would immediately cut NAND flash production by 30%. At the time NAND was selling below cost for spot prices as low as 31 cents/GB.
The Memory Guy questioned both the wisdom of the move and its authenticity in a blog post at that time, since this level of cut would reduce Toshiba’s market share while increasing its Continue reading “A Retrospect of Toshiba’s NAND Production Cut”
On Tuesday the HMC Consortium (that’s short for “Hybrid Memory Cube”) announced that members have agreed upon a specification. The consortium has been moving rapidly, meeting its targets despite the revolutionary nature of the interface.
As a reminder, this technology stacks multiple DRAMs in a single package with a logic chip at the base of the stack that performs all the signalling to the rest of the system. Signals between the DRAMs and logic chip use through-silicon vias (TSVs) as interconnections. This allows the technology to deliver 15 times the performance of DDR3 at only 30% of the power consumption. The Memory Guy first posted about the HMC in late 2011.
The consortium explains that the HMC interface already has 100 adopters, and that a few Continue reading “Hybrid Memory Cube Making Progress”
In a new cross-disciplinary effort, researchers have developed a novel approach to attach bonding wires to stacks of memory chips. The new technique, being called a “breakthrough” by its developers, promises to allow chips to be stacked to several times their current 8-chip and 16-chip heights.
At issue is the challenge of precisely bonding wires a fraction of the diameter of a human hair over great distances without their inadvertently coming into contact with their neighbors to create a short circuit. Such a short could destroy one or more of the chips in the stack, rendering the entire stack useless. The mechanical means of attaching these wires, although highly sophisticated, still has significant issues, that limit the economics of higher stacks.
Researchers at the Berea University of Geology (BUG) in Berea, Kentucky, noticed that certain Continue reading “New Memory Bonding Technique Shows Promise”
There’s been a lot of talk recently about increasing DRAM prices. Although this trend has been ongoing since late November (see chart) it has only recently garnered the attention of the press.
What is going on, and how is it likely to play out? The prices in the chart represent the lowest spot market prices reported by market tracker InSpectrum for the past year. These prices typically remain below contract prices as long as there is an oversupply, and stay above contract prices during a shortage.
According to InSpectrum’s figures, today’s lowest spot market DRAM prices are about double Continue reading “DRAM Prices on the Rise”
From time to time I am asked: “Why is NAND flash called NAND?” or “Why do we say RAM?” and similar questions. A lot of this has to do with history, and a lot of terminology which is now obsolete. To understand these strange names, you have to understand the history of memories. The Computer History Museum (CHM) in Silicon Valley is a great help in this vein.
Since the Memory Guy has been in Silicon Valley since 1977, a lot of this information is stored in my head. Let me try to share it with you in a way that I hope will make more sense, and will help outsiders to understand these odd names.
Here’s the history of memory nomenclature, as I understand it: Continue reading “Why Do Memories Have Those Odd Names?”