With all the new emerging memories that are being developed there must be quite a number of test runs to study exactly how well these new technologies and materials can perform. If a batch of 300mm wafers must be used for a single test then the cost multiplies, particularly if no other test can be run on that wafer.
Another great difficulty is that most memory manufacturers run their wafers on very high-efficiency and high-volume wafer fabs. It is perilous and wasteful to interrupt a production process to inject a batch of test wafers. Most fab managers would rather have a tooth pulled than to change their flow to accept an experimental lot.
What can be done to improve this situation?
Well the folks at Intermolecular, Inc. (IMI) explained to the Memory Guy that they have a solution: They have built a small fab that allows single wafers to be processed with varying parameters across a single wafer. In this way one wafer can be used to run 36 or more different experiments all at the same time. This is clearly more economical than having to run the experiment on 36 wafers or, even worse, 36 batches of wafers! Intermolecular says that, while production fabs are optimized for manufacturing, their fab is optimized for materials understanding.
The firm calls itself an Continue reading “Accelerating New Memory Materials Research”
Let’s look at how one form of 3D NAND is manufactured. For this post we will explore the original design suggested by Toshiba at the IEEE’s International Electron Device Meeting (IEDM) in 2007. It’s shown in the first graphic of this post. (Click on any of the graphics for a better view.)
Toshiba calls this technology “BiCS” for “Bit Cost Scaling.” The technique doesn’t scale the process the way the world of semiconductors has always done to date – it scales the cost without shrinking the length and width of the memory cell. It accomplishes this by going vertically, as is shown in this post’s first graphic.
This takes a special effort. This is where the real Continue reading “3D NAND: Making a Vertical String”
In the prior post we discussed the need to go vertically into the body of the die, since NAND flash can not be scaled much farther in length and width on the die’s surface. Toshiba invented a 3D NAND which has been adopted and refined by all flash makers. The idea is simple: Rather than shrink the cell’s length and width, why not turn the NAND string so that it’s standing on its end?
This concept is illustrated by this post’s first graphic, which was provided by Applied Materials. (Click on the graphic to see the whole thing at a larger size.) A standard NAND string that normally runs longitudinally is turned on its end to become a vertical string. Not only that, but it makes things easier if the string is split into two sections and Continue reading “What is a 3D NAND?”
A memory chip of a certain area costs about the same amount to produce, no matter how many bits it holds. Naturally, the more bits you can cram onto this chip, the cheaper the price per bit will be. Low cost is of the utmost importance in the world of memory.
Memory chip makers have shrunk the cost of a bit some nine orders of magnitude since the 1960s largely by shrinking the process, or “scaling” to increasingly tighter process geometries.
Flash has always been expected to reach a scaling limit. Over the past few generations technologists have developed Continue reading “Why Do We Need 3D NAND?”
Early this month I was invited to participate in Applied Materials’ (AMAT) Analyst Day. The sessions were rich in data covering the markets that would profit the company over the next few years.
Naturally, The Memory Guy fixated on those presentations that dealt with memory. When it came to the upcoming transition to 3D NAND, AMAT had a lot to say.
A later post will explain what 3D NAND actually is. Suffice it to say that today’s approach to making NAND flash has nearly reached its limit, and the approach that manufacturers plan to use in the future involves making NAND strings that stand on their ends. This has phenomenal implications on Continue reading “Applied’s Take on 3D NAND”