In a little 3-minute video released this week for the SEMICON West conference, Applied Materials dramatizes the 3D NAND manufacturing process by using hailstorms for atomic level deposition (ALD) and lightning bolts for etch, all while explaining that the wafer’s surface reaches temperatures hotter than the surface of the sun.
For those who already understand 3D NAND manufacture it’s an interesting Continue reading “Applied Materials Video Dramatizes 3D NAND Manufacture”
A very unusual side effect of the move to 3D NAND will be the impact on the equipment market. 3D NAND takes the pressure off of lithographic steps and focuses more attention on deposition and etch. The reason for going to 3D is that it provides a path to higher density memories without requiring lithographic shrinks.
This sounds like bad news for stepper makers like ASML, Canon, and Nikon while it should be a boon to deposition and etch equipment makers like Applied Materials, Tokyo Electron, and Lam Research.
In its summer 2013 V-NAND announcement, Samsung explained that it would be Continue reading “3D NAND’s Impact on the Equipment Market”
Let’s look at how one form of 3D NAND is manufactured. For this post we will explore the original design suggested by Toshiba at the IEEE’s International Electron Device Meeting (IEDM) in 2007. It’s shown in the first graphic of this post. (Click on any of the graphics for a better view.)
Toshiba calls this technology “BiCS” for “Bit Cost Scaling.” The technique doesn’t scale the process the way the world of semiconductors has always done to date – it scales the cost without shrinking the length and width of the memory cell. It accomplishes this by going vertically, as is shown in this post’s first graphic.
This takes a special effort. This is where the real Continue reading “3D NAND: Making a Vertical String”
In the prior post we discussed the need to go vertically into the body of the die, since NAND flash can not be scaled much farther in length and width on the die’s surface. Toshiba invented a 3D NAND which has been adopted and refined by all flash makers. The idea is simple: Rather than shrink the cell’s length and width, why not turn the NAND string so that it’s standing on its end?
This concept is illustrated by this post’s first graphic, which was provided by Applied Materials. (Click on the graphic to see the whole thing at a larger size.) A standard NAND string that normally runs longitudinally is turned on its end to become a vertical string. Not only that, but it makes things easier if the string is split into two sections and Continue reading “What is a 3D NAND?”
A memory chip of a certain area costs about the same amount to produce, no matter how many bits it holds. Naturally, the more bits you can cram onto this chip, the cheaper the price per bit will be. Low cost is of the utmost importance in the world of memory.
Memory chip makers have shrunk the cost of a bit some nine orders of magnitude since the 1960s largely by shrinking the process, or “scaling” to increasingly tighter process geometries.
Flash has always been expected to reach a scaling limit. Over the past few generations technologists have developed Continue reading “Why Do We Need 3D NAND?”
Early this month I was invited to participate in Applied Materials’ (AMAT) Analyst Day. The sessions were rich in data covering the markets that would profit the company over the next few years.
Naturally, The Memory Guy fixated on those presentations that dealt with memory. When it came to the upcoming transition to 3D NAND, AMAT had a lot to say.
A later post will explain what 3D NAND actually is. Suffice it to say that today’s approach to making NAND flash has nearly reached its limit, and the approach that manufacturers plan to use in the future involves making NAND strings that stand on their ends. This has phenomenal implications on Continue reading “Applied’s Take on 3D NAND”