The Memory Guy

Readers who have been following this series will note that The Memory Guy has so far described everything pertaining to emerging memory technologies except for the market outlook.  In this post I will share some key elements of our emerging memory forecast.

Since this is a simple blog post the forecast coverage is brief.  The detailed forecast appears in the report that is the basis of this blog post series: Emerging Memories Poised to Explode.

The first large-scale applications poised to replace today’s standard NOR flash with a new memory technology will be the embedded memories in CMOS logic chips that are processed on advanced process nodes (processes of 28nm and smaller.)  Many CMOS logic chips use NOR flash, especially microcontrollers (MCUs) which are found in a very broad range of applications.  The vast majority of MCUs, though, are uncomplicated and can therefore be economically produced on larger, older process nodes like 90nm and greater.

At tighter processes flashless versions of some MCUs already ship that can Continue reading →

Most memory industry participants view emerging memories as the eventual path of the business: There’s no doubt that today’s memory technologies will stop scaling, and that new memory technologies will need to replace today’s leading technologies both in the embedded and stand-alone spaces.  This includes DRAM, NAND flash, NOR flash, and SRAM.  Because this outlook is held by nearly everyone in the industry, all major memory manufacturers are investing in alternative memory technologies.  The leading players are researching multiple technologies at the same time.

Meanwhile, the industry outlook has allowed many university research projects and other similar efforts to gain funding to develop new memory types, spawning a large number of small single-technology companies tightly focused on one technology or another: ReRAM, MRAM, FRAM, and others, including such highly-differentiated technologies as carbon nanotubes and printable polymers.

In our Emerging Memory report Tom Coughlin and I did our Continue reading →

Something that distinguishes the Emerging Memory report that Tom Coughlin and I recently published is the depth in which we cover in the field.  This is not measured in pages, but in the topics that we cover.  For example, this blog post, excerpted from the report, covers the changes in tooling that will be necessary to allow a standard CMOS wafer fabrication plant (a “fab”) to produce an emerging memory technology, and the impact that this is likely to have on the market for semiconductor tools.

All of the emerging memory technologies covered in the Memory Guy’s previous post share certain things in common.  One of them is that they are built between metal layers, rather than in the silicon CMOS substrate itself (with the possible exception of the hafnium oxide FRAM.)

This means that the tooling required for any of these technologies will bear a strong resemblance to that used by any of the others.  For the most part these tools will be used for deposition and etch.  The lithography requirements will be satisfied by the tools used to pattern the metal layers.

The process flow in this figure sheds some light on the steps that Continue reading →

Here in the US we use an extremely odd expression.  If there are multiple varieties of an item we commonly say: “There are more of them than you can shake a stick at!”  This is a very lengthy way to say: “numerous.”  (I don’t believe that ANYONE understands how that expression became a part of our vernacular!)  Although The Memory Guy isn’t normally seen shaking a stick, I find it an apt way to describe the numerous new memory technologies that are being pioneered today.  There are certainly lots of them!

This post is intended to be very high-level technical description of today’s leading emerging memory technologies.  These are excerpts of the in-depth descriptions that can be found in our recently-released report: Emerging Memories Poised to Explode.

PCM: Also known as PRAM, Phase-Change Memory technology is based upon a material that can be either amorphous or crystalline at normal ambient temperatures.  The crystalline state has a low resistance and the amorphous state has a high resistance.  This is controlled by melting the bit cell by passing a current though it and then allowing it to cool at different rates.

In chemistry and physics, anything with a Continue reading →

Non-silicon memory technologies have been studied for about as long as have silicon-based technologies, but the silicon technologies have always been preferred.  Why is that, and why should anything change?

This is a question that The Memory Guy is often asked.  The answer is relatively simple.

Silicon memory technologies benefit from the fact that they have always been manufactured on process technologies that are nearly identical to those used to produce CMOS logic, and can therefore take advantage of the advancements that are jointly developed for both memory and logic processes.  In fact, before the middle 1980s, logic and memory processes were identical.  It wasn’t until then that the memory market grew large enough (over $5 billion/year) that it could support any additional process development on its own.

Even so, memory processes and logic processes are more similar than different.  This synergy between memory and logic continues to reduce the process development cost for both memories and logic.

Emerging memories depart from Continue reading →