NAND Flash - The Memory Guy Blog

Why Facebook Can’t Get its Dream Memory Chip

During the Flash Memory Summit last August Facebook’s Jason Taylor, Director of Capacity Engineering and Analysis, asked in his keynote speech for a flash chip with dramatically lower cost per gigabyte, saying that he would readily give up speed and endurance to achieve this lower cost. Taylor called this “Cold Flash” and said he was willing to use something that was “Write Once, Read Many” or WORM for data that was unlikely to change over its lifetime. He said this was Facebook’s “Ask of the Industry.”

That same sentiment was echoed yesterday at Samsung’s Memory Solutions Forum by eBay’s Distinguished Engineer and Technologist Roark Hilomen, who said that he could live with 1/3rd the number of writes that normal flash supports as long as he could get it for 1/4 the price.

Unfortunately this is simply not possible.

Let’s do a little math to understand Continue reading “Why Facebook Can’t Get its Dream Memory Chip”

Hynix Squeaks Out Another Update

In its own uniquely minimalistic style, Hynix has updated the status of the second line of its Wuxi fab, the one that was hit by a fire on September 4:

We would like to provide the following update on the recovery status of SK Hynix Wuxi fab that was affected by the fire on Wednesday September 4, 2013. The air ventilation system and cleanroom in the line that was affected by the fire have now been substantially restored, and we have resumed partial utilization in this line from Thursday October 10, 2013. We will gradually raise utilization and make every effort to recover normalized level of pre-fire utilization in November as planned.

This statement should put to rest Continue reading “Hynix Squeaks Out Another Update”

Samsung Announces 3D NAND Production

Samsung has announced production of its 3D NAND technology. This approach, first introduced by Toshiba in 2007, allows NAND flash makers to achieve more bits per chip by building NAND strings, which normally run across the surface of the chip, as vertical stacks.

It’s a fascinating technology, since it harnesses exotic steps invented by DRAM makers in the 1990s to get over scaling problems in that technology. At the time DRAM had to go vertical to follow Moore’s Law and there were two schools of vertical DRAM: Stacked Capacitor, and Trench Cell. The stacked capacitor camp layered polysilicon and silicon dioxide into layers to form a vertical capacitor. The trench camp etched a very narrow and deep hole into the silicon and lined it with the capacitor plates. Both worked very well, but over time the trench makers have Continue reading “Samsung Announces 3D NAND Production”

Micron NAND Reaches 16nm

Micron has announced that it is sampling a new 128Gb NAND flash chip based upon a 16nm process, with production slated for the fourth quarter. To The Memory Guy’s knowledge this is the tightest process available.

The company, with its partner Intel, gained a lead with its 20nm process generation through its use of a Hi-k tunnel dielectric, a new material that replaces more conventional silicon dioxide layer with a new material (Micron won’t say what) that yields the same capacitance with a thinner layer. This has become very important with today’s tight processes because of issues of inter-cell interference.

Other NAND makers are migrating to Continue reading “Micron NAND Reaches 16nm”

Applied’s Take on 3D NAND

Early this month I was invited to participate in Applied Materials’ (AMAT) Analyst Day. The sessions were rich in data covering the markets that would profit the company over the next few years.

Naturally, The Memory Guy fixated on those presentations that dealt with memory. When it came to the upcoming transition to 3D NAND, AMAT had a lot to say.

A later post will explain what 3D NAND actually is. Suffice it to say that today’s approach to making NAND flash has nearly reached its limit, and the approach that manufacturers plan to use in the future involves making NAND strings that stand on their ends. This has phenomenal implications on Continue reading “Applied’s Take on 3D NAND”

SanDisk & Toshiba to Add NAND Capacity

SanDisk today announced that its joint venture with Toshiba would begin construction in August of its Fab 5 “phase two” shell. Completion of this Yokkaichi, Japan wafer fabrication facility is slated for mid-2014.

SanDisk expects to use this facility for technology transitions of existing Yokkaichi wafer capacity. The new clean room will provide the space for the additional equipment necessary to transition existing wafer capacity to next-generation 2D NAND technologies and to early generations of 3D NAND technology. In this way it will perform support for Fab 3, Fab 4 and phase one of Fab 5.

This is consistent with the JV’s use of Continue reading “SanDisk & Toshiba to Add NAND Capacity”

SanDisk & Toshiba Move to Next Process Node

SanDisk and Toshiba, in separate announcements, both today disclosed their next-generation process technology.

The companies introduced their new “1y” processing node that, according to SanDisk, produces 19nm x 19.5nm cell, versus the earlier “19nm” process (or “1x”) that used a 19nm x 26nm cell.

The graphic for this post (click to enlarge) was presented during SanDisk’s May 5th Analyst Day and compares the 24nm process to the 19 x 26nm process, moving to the 19 x 19nm process, and eventually to “1z” which neither company is yet revealing. After the 1z process SanDisk believes Continue reading “SanDisk & Toshiba Move to Next Process Node”

A Retrospect of Toshiba’s NAND Production Cut

There are some who still believe that Toshiba made good on its announcement to cut NAND flash production by 30%. Let’s take a close look to see if that really happened.

Readers may recall that Toshiba stated last July that it would immediately cut NAND flash production by 30%. At the time NAND was selling below cost for spot prices as low as 31 cents/GB.

The Memory Guy questioned both the wisdom of the move and its authenticity in a blog post at that time, since this level of cut would reduce Toshiba’s market share while increasing its Continue reading “A Retrospect of Toshiba’s NAND Production Cut”

Why Do Memories Have Those Odd Names?

From time to time I am asked: “Why is NAND flash called NAND?” or “Why do we say RAM?” and similar questions. A lot of this has to do with history, and a lot of terminology which is now obsolete. To understand these strange names, you have to understand the history of memories. The Computer History Museum (CHM) in Silicon Valley is a great help in this vein.

Since the Memory Guy has been in Silicon Valley since 1977, a lot of this information is stored in my head. Let me try to share it with you in a way that I hope will make more sense, and will help outsiders to understand these odd names.

Here’s the history of memory nomenclature, as I understand it: Continue reading “Why Do Memories Have Those Odd Names?”

Macronix Solves Flash Wear Problem

The December issue of the IEEE Spectrum includes a fascinating article about a 100 million cycle flash memory developed by Macronix. The company will present this design at at IEDM this month.

In brief: Macronix’ researchers buried a heater in the array to heat the tunnel dielectric, annealing out the disruptions & traps that might cause a bit to fail.

A prototype has so far been tested more than 100 million cycles and it shows no sign of impending failure. Researchers believe that it is likely to reach one billion or more cycles, but such testing will take several months. This just may be able to Continue reading “Macronix Solves Flash Wear Problem”