This post is the first of a two-part series explaining commodities, and especially how they relate to memory chips. Part 1 defines a commodity and explains its attributes. Part 2 explains the commodity cycle.
Often in my presentations The Memory Guy will refer to memory chips, particularly DRAM and NAND flash, as Continue reading “Are Memory Chips Commodities? (Part 1)”
Today, Groundhog’s Day, Objective Analysis is publishing another five of our Objective Analysis Briefs, rounding out 2022’s total of new documents to 20. This week’s set covers even a more diverse range than those that we published in the past three weeks, with no overlap between any two Briefs’ subjects. They range from forecast methodology and China’s semiconductor efforts to critically considering Continue reading “Five More New Briefs Published”
Something that has really changed over the past few years is the use of an increasing numbers of voltage levels in multi-level cell flash, from SLC, to MLC, to TLC, and then QLC, with the promise of PLC (5 bits per cell) in the foreseeable future. That means each PLC cell must be able to hold 32 voltage levels accurately, and the NAND chip’s control logic must be able to tell one level from the next. This post’s graphic is intended to Continue reading “How 3D NAND Makes QLC and PLC Feasible”
This week’s newly-published Objective Analysis Briefs have just been released. These five cover business strategies (Intel, WDC, and Everspin), policy issues, and quantum computing – quite a variety! Each is derived from one of our most interesting and timeless “Insights” published on membership website Smartkarma. Now Objective Analysis is making these studies available to Continue reading “This Week’s Round of Objective Analysis Briefs”
This week five more Objective Analysis Briefs have just become available. This handful covers commonly held myths and the basic underpinnings of semiconductor market cycles. All are drawn from the most interesting and timeless of the Insights that we have published on membership website Smartkarma. Now Objective Analysis is providing them to our friends for a reasonable price.
The Brief is a very Continue reading “More New Objective Analysis Briefs Available”
Although Objective Analysis has published its “Brief” format white papers for some time, this line has never received the focus that it deserves. To remedy that, we are taking the most interesting and timeless of the Insights that we have published on membership website Smartkarma and providing them to our friends for a reasonable price.
The Brief is a very short report format used to make a succinct Continue reading “Introducing New Objective Analysis Briefs”
During his December 15 IEDM keynote speech, Samsung Electronics Chairman Kinam Kim really surprised me. He spoke favorably of the approach that YMTC is using to produce 3D NAND flash.
This approach, which YMTC named “Xtacking,” involves the use of two separate wafers to manufacture a 3D NAND chip. The brief way to describe it is to say that Continue reading “Did Samsung Just Endorse YMTC’s Xtacking?”
If you ask any two people in the computing industry to define the term “Storage Class Memory” you’re likely to get three or more answers. That’s because the term isn’t well defined anywhere.
Some people use it for emerging memory technologies like MRAM, ReRAM, FRAM, and PCM/XPoint. Others include NAND flash, even in the form of Continue reading “What Exactly IS “Storage Class Memory”?”
From time to time The Memory Guy is asked to explain why the NAND flash business doesn’t immediately convert to the next larger number of bits per cell once it becomes available. Many people tend to think that a significant cost benefit will necessarily result from migrating to the next number of bits. It surprises these folks to find that the cost advantage of moving from TLC to QLC is only half as great as the benefit of moving from SLC to MLC.
There is a diminishing Continue reading “SLC to MLC to TLC to QLC to PLC: Diminishing Returns”
For some time two sides of the computing community have been at odds. One side aims to add layers to the memory/storage hierarchy while other side is trying to halt this growth.
This has been embodied by recent attempts to stop using objective nomenclature for cache layers (L1, L2, L3) and moving to more subjective names that aim to limit any attempt to add another new layer.
This is a matter close to my heart, since Continue reading “Putting the Brakes on Added Memory Layers”