How 3D NAND Makes QLC and PLC Feasible

Four groups of dots representing the number of voltage levels in MLC, TLC, QLC, and PLC flash.Something that has really changed over the past few years is the use of an increasing numbers of voltage levels in multi-level cell flash, from SLC, to MLC, to TLC, and then QLC, with the promise of PLC (5 bits per cell) in the foreseeable future.  That means each PLC cell must be able to hold 32 voltage levels accurately, and the NAND chip’s control logic must be able to tell one level from the next.  This post’s graphic is intended to Continue reading “How 3D NAND Makes QLC and PLC Feasible”

This Week’s Round of Objective Analysis Briefs

Five briefs on top of each otherThis week’s newly-published Objective Analysis Briefs have just been released.  These five cover business strategies (Intel, WDC, and Everspin), policy issues, and quantum computing – quite a variety!  Each is derived from one of our most interesting and timeless “Insights” published on membership website Smartkarma.  Now Objective Analysis is making these studies available to Continue reading “This Week’s Round of Objective Analysis Briefs”

More New Objective Analysis Briefs Available

Five briefs on top of each otherThis week five more Objective Analysis Briefs have just become available.  This handful covers commonly held myths and the basic underpinnings of semiconductor market cycles.  All are drawn from the most interesting and timeless of the Insights that we have published on membership website Smartkarma.  Now Objective Analysis is providing them to our friends for a reasonable price.

The Brief is a very Continue reading “More New Objective Analysis Briefs Available”

Introducing New Objective Analysis Briefs

Five briefs on top of each otherAlthough Objective Analysis has published its “Brief” format white papers for some time, this line has never received the focus that it deserves.  To remedy that, we are taking the most interesting and timeless of the Insights that we have published on membership website Smartkarma and providing them to our friends for a reasonable price.

The Brief is a very short report format used to make a succinct Continue reading “Introducing New Objective Analysis Briefs”

Did Samsung Just Endorse YMTC’s Xtacking?

Closeup of Samsung graphic, showing illustration of wafer-bonded NANDDuring his December 15 IEDM keynote speech, Samsung Electronics Chairman Kinam Kim really surprised me.  He spoke favorably of the approach that YMTC is using to produce 3D NAND flash.

This approach, which YMTC named “Xtacking,” involves the use of two separate wafers to manufacture a 3D NAND chip.  The brief way to describe it is to say that Continue reading “Did Samsung Just Endorse YMTC’s Xtacking?”

What Exactly IS “Storage Class Memory”?

Single-quadrant chart with Bandwidth runing horizontally and cost vertically. Shows where HDD, DRAM, and NAND flash fit, and has an undefined Storage Class Memory block in the center.If you ask any two people in the computing industry to define the term “Storage Class Memory” you’re likely to get three or more answers.  That’s because the term isn’t well defined anywhere.

Some people use it for emerging memory technologies like MRAM, ReRAM, FRAM, and PCM/XPoint.  Others include NAND flash, even in the form of Continue reading “What Exactly IS “Storage Class Memory”?”

SLC to MLC to TLC to QLC to PLC: Diminishing Returns

Chart shows asymptotically diminishing cost reductions achieved by migrating from SLC to MLC to TLC to QLC to PLCFrom time to time The Memory Guy is asked to explain why the NAND flash business doesn’t immediately convert to the next larger number of bits per cell once it becomes available.  Many people tend to think that a significant cost benefit will necessarily result from migrating to the next number of bits.  It surprises these folks to find that the cost advantage of moving from TLC to QLC is only half as great as the benefit of moving from SLC to MLC.

There is a diminishing Continue reading “SLC to MLC to TLC to QLC to PLC: Diminishing Returns”

Putting the Brakes on Added Memory Layers

Close-up of a part of the blog post's main graphicFor some time two sides of the computing community have been at odds.  One side aims to add layers to the memory/storage hierarchy while other side is trying to halt this growth.

This has been embodied by recent attempts to stop using objective nomenclature for cache layers (L1, L2, L3) and moving to more subjective names that aim to limit any attempt to add another new layer.

This is a matter close to my heart, since Continue reading “Putting the Brakes on Added Memory Layers”

Why 3D NAND is Stuck at 40nm

Top-Down look at a 3D NAND column with its concentric rings of materialsI recently was asked how much 3D NAND pitches had shrunk since the technology’s 2013 introduction.  Samsung made a big to-do about using 40nm back in 2015, but the company and its competitors don’t seem to have given an update since then.  Shouldn’t it have gone to smaller processes like 35nm, 25nm, 20nm, etc.?

The Memory Guy’s reply was that it’s nearly impossible Continue reading “Why 3D NAND is Stuck at 40nm”

The Invention of Charge Trap Memory – John Szedon

Cartoon of a 4-layer 3D NAND with word balloons speling out the different partsA significant transition has occurred over the past few years that many people don’t know about: Flash memory has moved almost wholesale from the floating gate bit cells, the process that they had always used before, to charge trap bit cells.

Until 2002 all flash used a floating gate.  That year partners AMD & Fujitsu, who later merged Continue reading “The Invention of Charge Trap Memory – John Szedon”