This week the International Solid State Circuits Conference (ISSCC) was held in San Francisco. What was there? The Memory Guy will tell you!
There were three NAND flash papers, one each from Toshiba, Samsung, and Western Digital Corp. (WDC).
Toshiba described a 96-layer QLC 1.33 terabit chip. Like the chip that Toshiba presented last year, this one uses CUA, which Toshiba calls “Circuit Under Array” although Micron, who originated the technology, says that CUA stands for “CMOS Under Array.” Toshiba improved the margins between the cells by extending the gate threshold ranges below zero, a move that forced them to re-think the sense amplifiers. They also implemented a newer, faster, lower-error way to Continue reading “Memory Sightings at ISSCC”
For more than a year The Memory Guy has been fielding questions about Micron’s QuantX products.
First announced at the 2016 Flash Memory Summit, this brand name has been assigned to Micron SSDs and DIMMs that use the Intel/Micron 3D XPoint Memory. Originally QuantX products were scheduled to ship in 2017, but Micron is currently projecting availability in 2019. My clients wonder why there have been these delays, and why Micron is not more actively marketing this product.
The simple answer is that it doesn’t make financial sense for Micron to ship these products at this time.
Within two weeks of the first announcement of 3D XPoint Memory, at the 2015 Flash Memory Summit, I knew and explained that the technology would take two years or more to reach manufacturing cost parity with DRAM, even though Intel and Micron loudly proclaimed that it was ten times denser than DRAM. This density advantage should eventually allow XPoint manufacturing costs to drop below DRAM costs, but any new technology, and even old technologies that are in low-volume production, suffer a decided scale disadvantage against DRAM, which sells close Continue reading “Where is Micron’s QuantX?”
Why has Intel’s NVM Solutions Group (NSG), the owner of the company’s NAND flash, SSD, and 3D XPoint businesses, been losing money during a time when all other manufacturers are more profitable than they have been in years?
This is a question that certain investors have put to The Memory Guy for the past year or so, and it deserves some explanation.
This post’s graphic compares Intel’s NSG net profit margins to the margins published by other memory companies. (Click on it to see the whole chart.) This isn’t a completely clean comparison since the data for Samsung, SK hynix, and Micron includes DRAM, and recent quarters are missing for Western Digital (SanDisk) and Toshiba since these companies have stopped sharing comparable financials, but it still serves as a relatively clear indication that Intel’s NSG (blue) is losing money while all other companies are quite profitable.
Something seems dreadfully Continue reading “Intel’s Losses Amid Others’ Gains”
What really happens in NAND flash during an MLC, TLC, or QLC write? Although there are lots of websites that explain that multilevel cells store four, or eight, or sixteen different voltage levels on a cell (for MLC, TLC, or QLC), they don’t spell out the process of putting those voltage levels onto the bit cell.
Fortunately, Vic Ye, Manager, NAND Flash Characterization at Yeestor Microelectronics Co., Ltd. in Shenzhen, China presented the programming process in a series of short videos at the Flash Memory Summit last August. The Memory Guy was fortunate enough to attend his presentation. Yeestor is a fabless semiconductor manufacturer that manufactures flash storage controllers for SSDs (PCIe & SATA) and flash cards (SD, UFS, eMMC, etc.)
Mr. Ye later gave me permission to share his videos and these are the foundation of this post. They’re brief (13 seconds to 1:10) so they won’t take much time to review. The videos were a part of his slide presentation titled: A Graphical Journey into 3D NAND Program Operations that can be downloaded from The Flash Memory Summit website by clicking the presentation title above and entering your e-mail address.
A multilevel flash bit cell has Continue reading “Videos Demystify MLC NAND Programming”
It’s earnings call season, and we have heard of a slowing DRAM market and NAND flash price declines from Micron, SK hynix, Intel, and now Samsung. DRAM prices have stopped increasing, and that can be viewed as a precursor to a price decline.
Samsung’s 31 October, 2018 3Q18 earnings call vindicated Objective Analysis‘ forecast for a 2H18 downturn in memories that will take the rest of the semiconductor market with it.
Those familiar with our forecast know that for a few years we have been predicting a downturn in the second half of this year as NAND flash prices fall, followed by a DRAM price collapse. After the DRAM collapse the rest of the semiconductor market will undergo a downturn.
We’ve been calling for this downturn for some time. Dan Hutcheson at VLSI Research has been videotaping our forecast every December for the past Continue reading “Memory Market Falling, as Predicted”
Many readers have probably wondered why NAND flash fabs are so enormous. Although DRAM fabs used to be the largest, running around 60,000 wafers per month, NAND flash fabs now put that number to shame, running anywhere from 100,000-300,000 wafers per month. Why are they so huge?
The reason is that you need to run that many wafers to reach the optimum equipment balance. The equipment must be balanced or some of it will be sitting idle, and with some tools costing $50 million (immersion scanners) you want to minimize their idle time to the smallest possible number. I am sure that this is a tough problem, although I have never had to solve it myself.
The most important reason that so much attention is focused on this is that the cost of the wafer depends on the efficiency of the fab. If you built a $13 billion NAND flash fab that produced 90,000 wafers per month instead of 100,000 wafers per month, then the amount of investment per wafer would be 10% higher. That can make a significant difference to Continue reading “Why are NAND Flash Fabs so Huge?”
Conventional wisdom holds that SSDs will someday displace all HDDs, but in reality SSDs are proving to be more of a challenge to the DRAM market than to the HDD market.
Right now you are probably reviewing the date of this post to make sure it’s not dated April 1. I assure you that this is the truth. To understand it, though, you must look at a computer as a computer architect would, or, in other words, the way that an application program sees the memory/storage hierarchy.
To the application program there is no HDD and memory, there is only memory. The Virtual Memory system, a part of the operating system, hides the difference between the two by moving code and data into DRAM as it is needed and back onto the HDD when it is no longer important, without telling the application program that it is moving anything around. I like to tell people that the DRAM makes the HDD look fast, and the HDD makes the DRAM look big.
If you think of the DRAM as something that makes the HDD look fast, then additional DRAM should help to make the Continue reading “Why DRAM is Threatened by SSDs”
In an interesting twist to today’s ongoing DRAM shortage, the Fuzhou Intermediate People’s Court, Fujian Province, China today granted a preliminary injunction to prevent Micron’s Chinese subsidiaries from manufacturing, selling, or importing certain DRAM modules and solid state drives in China.
This injunction, according to a Micron press release, was filed without allowing Micron to present its defense, a process which Micron finds to be: “inconsistent with providing a fair hearing through appropriate legal processes and procedures.”
Micron’s customers in China will find that the DRAM shortage has just become even worse than it already was. Before today China’s government was concerned enough about the shortage’s rising DRAM prices to have launched a price fixing investigation only one month ago. One result of today’s decision will be that there will be less DRAM in China, and that will probably cause prices to rise even more.
What will be the impact to Micron? I find it unlikely that this injunction is likely to change any DRAM maker’s business much during a shortage. Any lack of Micron DRAM in China is likely to be serviced by Samsung and SK hynix, but since there’s a shortage, these companies will need to reduce their shipments outside of China to satisfy Continue reading “How to Worsen a DRAM Shortage”
The Memory Guy has found that some people get confused about the terminology surrounding flash “Layers” and “Levels,” Sometimes confusing the two, and often misunderstanding what each one means. This post is meant to be a low-level primer to address that confusion.
There are actually three places where such terminology is used: The number of chips in a package, the number of conductor/insulator pairs in 3D NAND, and the number of voltage levels stored on any single bit cell within the chip. I will address them in that order.
CHIP STACKING: Since the 1990s Both NAND and NOR flash chip makers have been stacking chips within a single plastic package. Originally this approach was used to reduce the size of thin flip phones like the Motorola Razr by stacking an SRAM chip on top of NOR flash, but soon afterwards NAND chips began to use the same approach to get incredible storage capacities into a single IC package or eMMC, or into a microSD card format. What began as 2-die stacks became 4, then 8, and now 16 high. This post’s photo illustrates an 8-high stack.
Since the height of a standard plastic package for a chip is smaller than a stack of 16 full-thickness dice the wafers had to be Continue reading “NAND Flash’s Layers of Layers of Layers”
3D NAND presents an interesting conundrum. To improve bit costs and continue along the path of Moore’s Law the layer count must increase. Unfortunately 3D NAND can’t benefit from lithographic scaling; it’s pretty much stuck at 40nm design rules forever. The natural way to reduce costs and increase chip density is by adding layers.
But adding layers increases the size of the staircase structure used to access the wordline layers.
With today’s structures, the addition of layers means adding stairs to the staircase – if you double the number of layers then the amount of die area required by the staircase doubles. At some point the staircase becomes so large that the die has fewer GB/mm² than a die with half as many layers.
An example of a staircase structure can be seen in the Continue reading “Solving 3D NAND’s Staircase Problem”