Samsung’s View on Charge Trap Flash

Samsung's Cheese analogy for Charge Trap FlashAt the Flash Memory Summit yesterday ES Jung, PhD, EVP & GM for the Samsung R&D Center, explained the inner workings of Samsung’s new V-NAND vertical NAND flash technology.  I will shortly be writing a series to explain what a 3D NAND is since there is little on the web that gives clear details about the technology.

One key attribute of most 3D NAND approaches is the use of a charge trapping layer.  This has to do with the difficulty of manufacturing sideways floating gates.

Dr Jung delighted the show’s audience by explaining that a standard floating gate is like Continue reading “Samsung’s View on Charge Trap Flash”

Samsung Announces 3D NAND Production

Toshiba's BiCS 3D NAND 2007 diagramSamsung has announced production of its 3D NAND technology.  This approach, first introduced by Toshiba in 2007, allows NAND flash makers to achieve more bits per chip by building NAND strings, which normally run across the surface of the chip, as vertical stacks.

It’s a fascinating technology, since it harnesses exotic steps invented by DRAM makers in the 1990s to get over scaling problems in that technology.  At the time DRAM had to go vertical to follow Moore’s Law and there were two schools of vertical DRAM: Stacked Capacitor, and Trench Cell.  The stacked capacitor camp layered polysilicon and silicon dioxide into layers to form a vertical capacitor.  The trench camp etched a very narrow and deep hole into the silicon and lined it with the capacitor plates.  Both worked very well, but over time the trench makers have Continue reading “Samsung Announces 3D NAND Production”

Applied’s Take on 3D NAND

Applied Materials expects for 3D NAND to grow the etch & CVD markets by 50%Early this month I was invited to participate in Applied Materials’ (AMAT) Analyst Day.  The sessions were rich in data covering the markets that would profit the company over the next few years.

Naturally, The Memory Guy fixated on those presentations that dealt with memory.  When it came to the upcoming transition to 3D NAND, AMAT had a lot to say.

A later post will explain what 3D NAND actually is.  Suffice it to say that today’s approach to making NAND flash has nearly reached its limit, and the approach that manufacturers plan to use in the future involves making NAND strings that stand on their ends.  This has phenomenal implications on Continue reading “Applied’s Take on 3D NAND”

Hynix and Spansion Join Forces

Spansion and SK Hynix AllianceSK Hynix and Spansion have announced a strategic NAND alliance under which Hynix will serve as a foundry for low-density SLC NAND chips made for Spansion using Hynix’ advanced processing nodes.

These products, aimed at the embedded market, should serve to strengthen Spansion in a market in which the company thrives. In fact,  Spansion expressed this very well in their press release, citing: “Spansion’s recognized customer support and commitment for longevity of supply, which is highly valued in the embedded market, where Spansion has established relationships.”

The new chips will be manufactured in “4x, 3x, and 2xnm” process technologies.

The companies have also agreed to cross-license their patent portfolios.

You may be asking yourself: “What does Hynix Continue reading “Hynix and Spansion Join Forces”

IBM to Build Micron Hybrid Memory Cube

Conceptual Cutaway Drawing of the Hybrid Memory CubeIn a December 1 press release IBM announced that the company will be manufacturing Micron Technology’s Hybrid Memory Cube (HMC) which IBM claims to be “the first commercial CMOS manufacturing technology to employ through-silicon vias (TSVs).”

This device is one that Altera, Intel, Micron, Open Silicon, Samsung, and Xilinx have all presented recently as a plausible solution to the difficulty of increasing the speed of DRAM/processor communications.  The Hybrid Memory Cube Consortium (HMCC) website offers a deep dive into the details of the consortium and the technology.

Continue reading “IBM to Build Micron Hybrid Memory Cube”