Only months after Samsung’s announcement of 3D memory production a new 4-dimensional memory has been prototyped by university researchers. This memory not only has bits in the X and Y dimensions, like planar NAND, and the Z dimension, like 3D NAND, but it also grows in capacity over time, spanning the fourth dimension: time.
This research has been spearheaded by George P. Burdell, Assistant Associate Professor pro tem at Death Valley University. The work is the culmination of a decades-long effort to find a way to increase memory sizes in systems without the need to replace chips or modules.
The team has created the name “Growing RAM” or “GRAM” for the technology. Current prototypes exhibit very favorable Continue reading “Researchers Devise 4-D Memory”
Everyone knows that flash memory is about to hit its scaling limit – it’s right around the corner. We’re ready for it because it’s been right around the corner for more than a decade now. It’s so close we can taste it.
When will it happen?
One thing that is quite clear is that nobody knows when NAND flash will stop scaling. Everyone knows that it’s soon, but researchers continue to find ways to push the technology another couple of process nodes past where anyone thought it could possibly go, and they have been doing this since Continue reading “The End of Flash Scaling”
At a Conference in San Francisco today (Tuesday December 13 ) ST-Ericsson and CEA-Leti presented a paper on something the companies called a: “Breakthrough 3DIC with Wide I/O Interface.”
This product appears to be a variation on the Hybrid Memory Cube, or HMC concept detailed in a prior post.
Remember that the HMC stacks a number of DRAM chips atop a logic chip. The memories store data and communicate to the logic chip through thousands of through-silicon vias (TSVs) while the logic chip handles communications with the outside world. Continue reading “WIOMING: Another Spin on the Hybrid Memory Cube”