The Memory Guy Blog - Jim Handy, Objective Analysis, on Semiconductor Memories

Extending the Write/Erase Lifetime of Phase Change Memory: Part 3 – Failure Modes for the Threshold Switch

This is Part 3 of a short Memory Guy series in which contributor Ron Neale continues to explore the possible future impact on PCM memory performance, especially write/erase endurance, building on the results of the IBM/Yale University analysis outlined in Part 1 and Part 2.

Part 3 of this series of articles triggered by the recently published PCM device analysis by a team from IBM/Yale University, moves to a look at its possible implications for the arsenic doped GST threshold switch. Although the threshold switch was not part of the IBM/Yale work, the implementation of the call for bipolar operation of PCMs means there will be a requirement for a threshold switch whose durability matches that of the memory with which it will be associated in a memory array.

If the study’s finding for PCM can be applied to the arsenic-doped GST threshold switch which is used in today’s commercially-available PCM arrays then the threshold switch might just be the weak link that accounts for the poor endurance of commercial PCM memory arrays.

One little conundrum we must address is: Which Continue reading “Extending the Write/Erase Lifetime of Phase Change Memory: Part 3 – Failure Modes for the Threshold Switch”

Why DRAM is Threatened by SSDs

Conventional wisdom holds that SSDs will someday displace all HDDs, but in reality SSDs are proving to be more of a challenge to the DRAM market than to the HDD market.

Right now you are probably reviewing the date of this post to make sure it’s not dated April 1. I assure you that this is the truth. To understand it, though, you must look at a computer as a computer architect would, or, in other words, the way that an application program sees the memory/storage hierarchy.

To the application program there is no HDD and memory, there is only memory. The Virtual Memory system, a part of the operating system, hides the difference between the two by moving code and data into DRAM as it is needed and back onto the HDD when it is no longer important, without telling the application program that it is moving anything around. I like to tell people that the DRAM makes the HDD look fast, and the HDD makes the DRAM look big.

If you think of the DRAM as something that makes the HDD look fast, then additional DRAM should help to make the Continue reading “Why DRAM is Threatened by SSDs”

Extending the Write/Erase Lifetime of Phase Change Memory: Part 2 – A More Complete View of Element Separation

This is Part 2 of a short Memory Guy series in which contributor Ron Neale continues to explore the possible future impact on PCM memory performance, especially write/erase endurance, building on the results of the IBM/Yale University analysis outlined in Part 1.

After, in Part 1, summarizing the methodology my next step was to try to bring together in another simple diagram all the detail of the complexity of the movement of the different elements of the phase change memory material at different locations within the memory cell which the IBM/Yale work has disclosed. Movement which leads to the conclusion that bi-polar operation would be means of extending PCM endurance.

In this post’s first diagram (below) the central region provides illustration of the paper’s unique PCM device structure: A high aspect ratio tapered cell lined with a metal conductor. With the two-state memory switching region located (red coloured) roughly at the centre of the taper. This means that, Continue reading “Extending the Write/Erase Lifetime of Phase Change Memory: Part 2 – A More Complete View of Element Separation”

How to Worsen a DRAM Shortage

In an interesting twist to today’s ongoing DRAM shortage, the Fuzhou Intermediate People’s Court, Fujian Province, China today granted a preliminary injunction to prevent Micron’s Chinese subsidiaries from manufacturing, selling, or importing certain DRAM modules and solid state drives in China.

This injunction, according to a Micron press release, was filed without allowing Micron to present its defense, a process which Micron finds to be: “inconsistent with providing a fair hearing through appropriate legal processes and procedures.”

Micron’s customers in China will find that the DRAM shortage has just become even worse than it already was. Before today China’s government was concerned enough about the shortage’s rising DRAM prices to have launched a price fixing investigation only one month ago. One result of today’s decision will be that there will be less DRAM in China, and that will probably cause prices to rise even more.

What will be the impact to Micron? I find it unlikely that this injunction is likely to change any DRAM maker’s business much during a shortage. Any lack of Micron DRAM in China is likely to be serviced by Samsung and SK hynix, but since there’s a shortage, these companies will need to reduce their shipments outside of China to satisfy Continue reading “How to Worsen a DRAM Shortage”

Extending the Write/Erase Lifetime of Phase Change Memory: Part 1- PCM Element Separation and Endurance

This is the first of a new line-up of Memory Guy posts by Ron Neale. In this 4-part series Ron takes a look at the recently-published analysis by a team from IBM and Yale University (Wiley: Communications of Advanced Materials, Volume 30, Issue 9, March 1, 2018 “Self-Healing of a Confined Phase Change Memory Device with a Metallic Surfactant Layer,” Xie et al) which has cast some new light on the complexity of the movement and element separation in phase change memory (PCM) device structures.

In this series of articles I will briefly review what I think is an important piece of work and its implications for the future of PCM write/erase (w/e) endurance in commercial PCM memory arrays. Today’s production Phase-Change Memory, the basis of the Intel/Micron 3D XPoint Memory, wears out faster than expected. This series will investigate some of the potential reasons for this discrepancy.

Back in 2016 a research team led by IBM claimed the world record for PCM w/e endurance of greater than 2 x 10E12 cycles (ALD-based Confined PCM with a Metallic Liner Toward Unlimited Endurance, Proc IEDM 2016 ). As of today commercially available PCM memory arrays offer w/e endurance of some six orders of magnitude less. The table below Continue reading “Extending the Write/Erase Lifetime of Phase Change Memory: Part 1- PCM Element Separation and Endurance”

NAND Flash’s Layers of Layers of Layers

The Memory Guy has found that some people get confused about the terminology surrounding flash “Layers” and “Levels,” Sometimes confusing the two, and often misunderstanding what each one means. This post is meant to be a low-level primer to address that confusion.

There are actually three places where such terminology is used: The number of chips in a package, the number of conductor/insulator pairs in 3D NAND, and the number of voltage levels stored on any single bit cell within the chip. I will address them in that order.

CHIP STACKING: Since the 1990s Both NAND and NOR flash chip makers have been stacking chips within a single plastic package. Originally this approach was used to reduce the size of thin flip phones like the Motorola Razr by stacking an SRAM chip on top of NOR flash, but soon afterwards NAND chips began to use the same approach to get incredible storage capacities into a single IC package or eMMC, or into a microSD card format. What began as 2-die stacks became 4, then 8, and now 16 high. This post’s photo illustrates an 8-high stack.

Since the height of a standard plastic package for a chip is smaller than a stack of 16 full-thickness dice the wafers had to be Continue reading “NAND Flash’s Layers of Layers of Layers”

Ron Neale To Share Posts

The Memory Guy is pleased to begin publishing posts from Ron Neale. Ron is a specialist in phase-change memory (PCM or PRAM) who has been contributing a lot of analysis of this technology in EE Times.

Ron’s career has centered around phase-change memory. He was the lead author for the groundbreaking 1970 PCM article in Electronics Magazine, co-authored by Intel’s Gordon Moore (of Moore’s Law fame) introducing the world’s first PCM, a 256-bit device.

Now that the Intel/Micron 3D XPoint Memory has been revealed to use the same technology as Numonyx’ NOR-compatible PCMs, Ron’s analysis of this technology is especially poignant.

Look for posts that feature his keen insight on the technology, its particular challenges, and the ways that PCM is applied to practical problems in advance computing.

Latest White Paper: New Memories for Efficient Computing

There has been a lot of discussion in the trade press lately about new memory technologies. This is with good reason: Existing memory technologies are approaching a limit after which bits can’t be shrunk any smaller, and that limit would put an end to Moore’s Law.

But there are even more compelling reasons for certain applications to convert from today’s leading technologies (like NAND flash, DRAM, NOR flash, SRAM, and EEPROM) to one of these new technologies, and that is the fact that the newer technologies all provide considerable energy savings in computing environments.

Objective Analysis has just published a white paper that can be downloaded for free which addresses a number of these technologies. The white paper explains why energy is wasted with today’s technologies and how these new memory types can dramatically reduce energy consumption.

It also provides a Continue reading “Latest White Paper: New Memories for Efficient Computing”

Storage/Memory Hierarchy 40 Years Ago

Last year I stumbled upon something on the Internet that I thought would be fun to share. It’s the picture on the left from a 1978 book by Laurence Allman: Memory Design Microcomputers to Mainframes. The picture’s not too clear, but it is a predecessor to a graphic of the memory/storage hierarchy that The Memory Guy often uses to explain how various elements (HDD, SSD, DRAM) fit together.

On the horizontal axis is Access Time, which the storage community calls latency. The vertical axis shows cost per bit. The chart uses a log-log format: both the X and Y axes are in orders of magnitude. This allows a straight line to be drawn through the points that represent the various technologies, and prevent most of the technologies from being squeezed into the bottom left corner of the chart.

What I find fascinating about this graphic is not only the technologies that it includes but also the way that it’s presented. First, let’s talk about the technologies.

At the very top we have RAM: “TTL, ECL, and fast MOS static types.” TTL and ECL, technologies that are seldom Continue reading “Storage/Memory Hierarchy 40 Years Ago”

Solving 3D NAND’s Staircase Problem

3D NAND presents an interesting conundrum. To improve bit costs and continue along the path of Moore’s Law the layer count must increase. Unfortunately 3D NAND can’t benefit from lithographic scaling; it’s pretty much stuck at 40nm design rules forever. The natural way to reduce costs and increase chip density is by adding layers.

But adding layers increases the size of the staircase structure used to access the wordline layers.

With today’s structures, the addition of layers means adding stairs to the staircase – if you double the number of layers then the amount of die area required by the staircase doubles. At some point the staircase becomes so large that the die has fewer GB/mm² than a die with half as many layers.

An example of a staircase structure can be seen in the Continue reading “Solving 3D NAND’s Staircase Problem”