Crosspoint

Emerging Memories Today: Process Equipment Requirements

Emerging Memory ParadeSomething that distinguishes the Emerging Memory report that Tom Coughlin and I recently published is the depth in which we cover in the field.  This is not measured in pages, but in the topics that we cover.  For example, this blog post, excerpted from the report, covers the changes in tooling that will be necessary to allow a standard CMOS wafer fabrication plant (a “fab”) to produce an emerging memory technology, and the impact that this is likely to have on the market for semiconductor tools.

All of the emerging memory technologies covered in the Memory Guy’s previous post share certain things in common.  One of them is that they are built between metal layers, rather than in the silicon CMOS substrate itself (with the possible exception of the hafnium oxide FRAM.)

This means that the tooling required for any of these technologies will bear a strong resemblance to that used by any of the others.  For the most part these tools will be used for deposition and etch.  The lithography requirements will be satisfied by the tools used to pattern the metal layers.

The process flow in this figure sheds some light on the steps that Continue reading

Emerging Memories Today: The Technologies: MRAM, ReRAM, PCM/XPoint, FRAM, etc.

Emerging Memory ParadeHere in the US we use an extremely odd expression.  If there are multiple varieties of an item we commonly say: “There are more of them than you can shake a stick at!”  This is a very lengthy way to say: “numerous.”  (I don’t believe that ANYONE understands how that expression became a part of our vernacular!)  Although The Memory Guy isn’t normally seen shaking a stick, I find it an apt way to describe the numerous new memory technologies that are being pioneered today.  There are certainly lots of them!

This post is intended to be very high-level technical description of today’s leading emerging memory technologies.  These are excerpts of the in-depth descriptions that can be found in our recently-released report: Emerging Memories Poised to Explode.

PCM: Also known as PRAM, Phase-Change Memory technology is based upon a material that can be either amorphous or crystalline at normal ambient temperatures.  The crystalline state has a low resistance and the amorphous state has a high resistance.  This is controlled by melting the bit cell by passing a current though it and then allowing it to cool at different rates.

In chemistry and physics, anything with a Continue reading

Emerging Memories Today: Understanding Bit Selectors

Emerging Memory ParadeThe previous post in this series (excerpted from the Objective Analysis and Coughlin Associates Emerging Memory report) explained why emerging memories are necessary.  Oddly enough, this series will explain bit selectors before defining all of the emerging memory technologies themselves.  The reason why is that the bit selector determines how small a bit cell can get, and that is a very significant component of the overall cost of the technology.  Cost, of course, is extraordinarily important because no system designer would use a component that would make a system more expensive than it absolutely needs to be!

A number of the Memory Guy’s readers may never have heard of a selector. I’ll explain it here.  It’s not complicated.

Every bit cell in a memory chip requires a selector.  This device routes the bit cell’s contents onto a bus that eventually makes its way to the chip’s pins, allowing it to be read or written.  The bit cell’s technology determines the type of selector that is appropriate: SRAMs use two transistors, DRAMs use one transistor, and flash memories combine a transistor with the Continue reading

Emerging Memories Today: Why Emerging Memories are Necessary

Emerging Memory ParadeNon-silicon memory technologies have been studied for about as long as have silicon-based technologies, but the silicon technologies have always been preferred.  Why is that, and why should anything change?

This is a question that The Memory Guy is often asked.  The answer is relatively simple.

Silicon memory technologies benefit from the fact that they have always been manufactured on process technologies that are nearly identical to those used to produce CMOS logic, and can therefore take advantage of the advancements that are jointly developed for both memory and logic processes.  In fact, before the middle 1980s, logic and memory processes were identical.  It wasn’t until then that the memory market grew large enough (over $5 billion/year) that it could support any additional process development on its own.

Even so, memory processes and logic processes are more similar than different.  This synergy between memory and logic continues to reduce the process development cost for both memories and logic.

Emerging memories depart from Continue reading

Emerging Memories Today: New Blog Series

Emerging Memory ParadeThere’s never been a more exciting time for emerging memory technologies. New memory types like PCM, MRAM, ReRAM, FRAM, and others have been waiting patiently, sometimes for decades, for an opportunity to make a sizeable markets of their own.  Today it appears that their opportunity is very near.

Some of these memory types are already being manufactured in volume, and the established niches that these chips sell into can provide good revenue.  But the market is poised to experience a very dramatic upturn as advanced logic processing nodes drive sophisticated processors and ASICs to adopt emerging persistent memory technologies.  Meanwhile Intel has started to aggressively promote its new 3D XPoint memory for use as a persistent (nonvolatile) memory layer for advanced computing.  It’s no wonder that SNIA, JEDEC, and other standards bodies, along with the Linux community and major software firms are working hard to implement the necessary standards and ecosystems to support widespread adoption of the persistent nature of these new technologies.

This post introduces a Continue reading

Making Sense of Intel & Micron’s XPoint Breakup

Micron-Intel 3D XPoint Memory InternalsOn Monday, July 16, Intel and Micron announced the termination of the two companies’ 3D XPoint Memory development efforts.  The companies will complete development of the second-generation product after which the IMFT Lehi, Utah facility will continue to manufacture the product but the two companies will no longer co-develop new versions of the 3D XPoint Memory.

Most readers haven’t been watching this business as carefully as The Memory Guy, and are puzzled by the move.  I will share what I know in an attempt to make the decision a little clearer.

Three years ago in July 2015 the two companies held an event to launch 3D XPoint Memory technology.  This upcoming technology would be 1,000 times faster than flash, and provide 1,000 times the endurance, on a chip that was 10 times as dense as “Standard Memory,” which everyone was to infer was DRAM.  This last implied that the technology would sell for a lower price than DRAM, and that’s the most important way that a technology that’s slower than DRAM can gain acceptance in a Continue reading

Intel Developer Forum – Not Much 3D XPoint Progress

IDF16 FaceAfter a big 3D XPoint launch one year ago almost anyone would expect for Intel to have had a lot of exciting new news to share about the technology at last week’s Intel Developer Forum (IDF).  Those who were watching for that, though, were in for a disappointment.

For readers who don’t remember, Intel and its partner, chipmaker Micron Technology, announced a new memory layer in July 2015 that would enable in-memory databases to expand well beyond the constraints posed by standard DRAM memory. The pair also boasted the additional benefit of being nonvolatile or persistent – data would not be lost if the power failed.  This technology promised to open new horizons in the world of computing.

Intel devoted a lot of effort to promotion and education during the following month’s IDF, and even demonstrated a prototype 3D XPoint SSD that performed seven to eight times as fast as Intel’s highest-performance existing NAND flash SSD – the DC S3700.  Although a DIMM form factor was disclosed, no prototypes were on hand.  Both were given the brand name “Optane”.

Moving forward one year to the 2016 IDF (the source of this post’s odd graphic), The Memory Guy was shown Continue reading

IBM Jumps on the “New Memory” Bandwagon

IBM's 3-Bit PCM Read AlgorithmAt a technical conference hosted by the IEEE this week IBM announced the results of nearly a decade of research in which its scientists have been investigating the emerging technology known as “Phase Change Memory” (PCM).  The scientists presented a means of successfully storing three bits per cell for the first time, while also addressing all of PCM’s challenging idiosyncrasies, including resistance drift and temperature drift.

Commonly referred to by the erroneous nickname “TLC” for Triple Level Cell, this technology squeezes three bits of data into the space of a single bit, essentially cutting the cost per gigabyte to about one third of that of a standard memory chip making it closer in cost to flash.

With this step IBM expects to help drive a new memory layer into existence, one that will fit between the cheap and slow NAND flash used in SSDs and the fast but expensive DRAM used for main memory.  Such a layer would improve the cost/performance of all types of Continue reading

Crossbar or Crosspoint?

Computing Crossbar SwitchThe Memory Guy has recently run across a point of confusion between two very similar terms: Crossbar and Crosspoint.

A crosspoint memory is a memory where a bit cell resides at every intersection of a wordline and a bitline.  It’s the smallest way you can make a memory cell.  Think of the wordlines and bitlines as the wires in a window screen.  If there’s a bit everywhere they cross, then it’s a crosspoint memory.

In most cases a crossbar is a communication path in a computing system.  (Of course, there are exceptions, the main one being a company, Crossbar Inc., that is developing a crosspoint memory technology!) A crossbar communication path is topographically similar to a crosspoint, but its function is to connect a number of memory arrays to a number of processors.  Visualize a vertical column of memory arrays named A, B, C… and a horizontal row of processors named 1, 2, 3… as is illustrated in this post’s graphic.  The crossbar can connect Processor 1 to Memory A, or to any other memory that is not already connected to another processor.  These connections are represented by the circles in the diagram.  You can see that this is an efficient way to allow processors to share a memory space to achieve very high speed inter-processor communications.

Crossbars are quite likely to Continue reading

Micron/Intel 3D XPoint Raises More Questions than Answers

Micron-Intel 3D XPoint Memory InternalsMicron and Intel hosted an event in San Francisco Tuesday, July 28, to introduce a new memory technology that they have named “3D XPoint”.  This technology was explained to be “up to 1,000 times faster, with 1,000 times the endurance of NAND flash” while being significantly cheaper than DRAM.

Some technical details:

  • 3D XPoint is a “Fundamentally Different Technology” than current memory types.  It’s an ReRAM that uses material property changes for bit storage where both DRAM and NAND use charge to store a bit
  • The chip currently stores 128Gb in two stacked planes of 64Gb each, storing a single bit per cell
    • Today’s densest production NAND flash chips store 128GB by using MLC, so this chip actually has twice as many bit cells as any production NAND flash
    • The companies do not see a clear limit to the number of planes they can stack, but are optimistic about this
  • The bulk mechanism can be used to store multiple bits on a single cell (MLC)
  • Today’s chip is made using a 20nm process, but can scale well past that
    • There is no clear limit of how far the technology can be scaled
  • It’s 1,000 times faster than NAND flash and offers 1,000 times NAND’s endurance
  • It’s 10 times as dense as today’s “Conventional Memory” (which I suppose to be DRAM)
  • This is not intended to replace either NAND or DRAM, but to coexist as a new memory layer between NAND and DRAM

The companies claim that other Continue reading